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ChipEstimate

  • Cadence at DAC 2011 – And Denali Party Update

    The 48 th Design Automation Conference ( DAC ) is just a little over one month away, and Cadence will have a substantial presence on the exhibit floor, in panel sessions, and in co-located workshops. Of course, the famous Denali Party is a highlight, and it is on! A new Cadence DAC microsite located...
    Posted to Industry Insights (Weblog) by rgoering on Mon, May 2 2011
  • ARM IP Talks! Keynote: Easing The Path To 32/28 nm

    Will the 32/28 nm process nodes ever go "mainstream," or will costs, complexity, and power problems put these nodes out of reach for all but a handful of users? High-k metal gate technology could make the difference, according to John Heinlein, vice president of marketing for ARM's Physical...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 15 2010
  • SoC and remodeling cost estimation

    Over at Cadence's Industry Insights blog by Richard Goering , he has a great writeup of a panel at the Virtual SoC Conference entitled "Are SoC Development Costs Significantly Underrated?" In it, there was a great analogy comparing a chip design project to a home remodeling project. This...
    Posted to Logic Design (Weblog) by Jack Erickson on Tue, Oct 6 2009
  • My Twitter Experiment - Just Follow Me

    "I didn't know that Conformal ECO-physical was released. When did that happen? Which version of LEC?" , said one of my customers said recently. I have a lot of customers who ask about the latest product information once in a while. I see my peeps at seminars, customer visits, workshops...
    Posted to Logic Design (Weblog) by Kenneth Chang on Tue, Mar 24 2009
  • Making the Right Decisions *Before* You Start Your Project

    Seems logical, but unfortunately, I run into customers today that grumble about their past experiences such as: "Gosh, I wish our chip wasn't so big. How did that happen?", says one ... "Our memory requirements grew and grew, out of control, almost couldn't fit it", says another...
    Posted to System Design and Verification (Weblog) by Kenneth Chang on Mon, Mar 23 2009
  • Build ASICs With a Strong Ecosystem: A New Paradigm

    Building ASICs is a pretty much standard process - you may define your specification based on whatever constraints you have, pick your IPs if any, do a guess-timate of your entire chip so you can figure out the budget, then commit - plunk down the cash and commit resources so you can really do the work...
    Posted to Logic Design (Weblog) by Kenneth Chang on Thu, Feb 5 2009
  • "I hate spreadsheets"

    So, as customer after customer visited the ChipEstimate booth on Oct. 1 (a tool for early chip planning as well as providing huge easy access to 1000's of IPs from 100's of 3rd party vendors for chip proto-building) during the very successful Power Forward Initiative (PFI) event in San Jose,...
    Posted to Logic Design (Weblog) by Kenneth Chang on Fri, Oct 3 2008
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