Home > Community > Tags > ChipEstimate.com/FPGA
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • Video: IP Ecosystem Helps Xilinx Become a “Platform Provider”

    Xilinx is making a shift from being a silicon provider to a platform provider, according to David Tokic, director of partner ecosystem alliances at Xilinx. As such, the company is increasingly relying on a broad ecosystem that includes silicon IP, EDA, and services. In a video interview at the recent...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 20 2011
Page 1 of 1 (2 items)