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  • back annotation via command line

    Is there any options that I can use command line interface to run back annotate to update the schematic using a .swp file? or is it possible to launch a particular schematic and then use an initialization file in that directory that commands the back-annotation.
    Posted to PCB Design (Forum) by powerit46 on Tue, Jan 25 2011
  • v163: how to change the capture image's size?

    I use allegro v16.3 to capture the current screen's status, but the capture image's size is too large for me, and is there any other argument or method to change the size? I can not change the Editor's size by "trapsize". so any suggestion? thanks for your kindly help!
    Posted to PCB SKILL (Forum) by pcbskill on Fri, Jan 7 2011
  • Creating Interconnection Cables/Custom Net Lists

    Hello, my company uses OrCAD 16.3 mainly for interconnecting components supplied by another company. We aren't using it for its logic control or compatibility with other programs. It's enough for us to connect pins to pins (with customized parts) to create an interconnection diagram. So, I need...
    Posted to PCB Design (Forum) by MadeInTheUSA on Thu, Dec 23 2010
  • How to Export Allegro Design Entry HDL to Capture?

    Hi Everyone, Please help to reply following the question. Thanks. How to Export Allegro Design Entry HDL to Capture? Victor
    Posted to PCB Design (Forum) by 741218 on Thu, Dec 16 2010
  • selecting part in capture

    hi , can any one tell me how to select part max7000 ic in capture place part section. thankyou
    Posted to PCB Design (Forum) by rakeshnettem on Fri, Oct 29 2010
  • OrCad Layout (v10.5) Design Reuse

    Hello, I have an existing board design consisting of two analog channels that are inputs to an A/D to a microcontroller. These analog channels consists of 6 SMT IC's with about 45 SMT discrete components (resistors, capacitors, diodes). Channel 1 is placed at right edge of tha board and Channel 2...
    Posted to Feedback, Suggestions, and Questions (Forum) by dmfulmer on Fri, Oct 15 2010
  • Orcad 16.2 - Create netlist error "CAP[0020]"

    Hi, I recently upgraded both computer,os and orcad. I am currently running Win 7- Orcad 16.2. Everything seems fine except for the creating a net list. The window flags me with " [CAP0020] Unable to open netlist format file:netlist.dll" I do see this .dll with the rest of the .dll files. Please...
    Posted to PCB Design (Forum) by Strickland on Sat, Sep 11 2010
  • Capture 16.3 Errors

    I'd like to report the following error in the 16.3 Version of Capture or Design Entry CIS: When converting a project from 16.01 to 16.3 Net Properties get mangled. I had a design all constrained with Propagation Delays and Relative Propagation Delays placed on a set of high-speed signal groups. When...
    Posted to PCB Design (Forum) by JWWS1 on Wed, Sep 8 2010
  • Old design from "Valid Logic Systems"

    I have a customer with an old design that was (as far as I can tell) created with Valid Logic System software for MAC OS in about 1993. They would like to view the content of the design some how. I can extract the logic (at the gate/FF level) from the output files but don't have a way to view the...
    Posted to Logic Design (Forum) by hap2 on Tue, Jul 27 2010
  • Re: OrCAD Capture hangs there forever when generating the PCB Editor netlist!

    The problem is not because of the user permission of Vista. The problem is solved by replacing all the Ls, Cs, and Rs in the design by new created components. All the Ls are with one L0402 footprint, the Cs with C0402, and the Rs with R0402.
    Posted to PCB Design (Forum) by Peyton on Wed, Jul 7 2010
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