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Virtuoso
Unleashing Mixed-Signal Tech on Tours (ToTs) in North America
At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The key challenges that our mixed-signal customers face...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Fri, Mar 29 2013
CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification
A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 9 2013
Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitment
Cadence holds a leading position in the EDA industry due to its broad product portfolio catering to digital and analog designs and the ever popular mixed-signal designs. With its immense technical and market leadership based on the Virtuoso platform for analog design and Encounter platform for digital...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Tue, Jan 8 2013
Mixed Signal Technology Summit Proceedings Now Available
In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...
Posted to
Mixed-Signal Design
(Weblog)
by
nizic
on Thu, Dec 13 2012
Video Keynote – Research Pushes Silicon to 60 GHz and Beyond
Can silicon run at 60-240 GHz with good performance and energy efficiency? Yes, according to Ali Niknejad , professor of electrical engineering and computer science at the University of California at Berkeley. In a keynote speech at the Mixed-Signal Technology Summit at Cadence in September, now available...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Dec 10 2012
Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and 20nm Leadership
A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press release is titled " TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Fri, Oct 19 2012
Learn From Expert Designers at Mixed-Signal Technology Summit
If you're involved in any phase of mixed-signal design and verification -- or someday might be -- you'll find a lot of valuable, practical information at the Cadence Mixed-Signal Technology Summit Sept. 20, 2012 in San Jose, California. In addition to Cadence R&D experts, you'll hear...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 30 2012
Designer View – Automating Analog Design with Intent Capture
Analog design is almost entirely a manual effort, and that needs to change, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, Daglio shows how analog/mixed-signal constraint capture and propagation can be automated,...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 15 2012
Panel: Integrating Low-Power ARM Processors into Mixed-Signal Designs
Mixed-signal chip designs with embedded digital signal processing are becoming more and more commonplace these days. How can you bring low-power processors, such as the ARM Cortex-M0 , into such designs quickly and efficiently? A lunch panel discussion at the recent Design Automation Conference (DAC...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 20 2012
DVCon User Panelists: Is Low Power Design Worth the Costs?
Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 29 2012
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