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Cadence,layout,error

  • VIRTUOSO GXL Auto-Place & Route problems

    Hi, I am using the student version of cadence tools at my Univ to auto place and route a custom design, using standard-cells. I am using the Custom IC tools suggested, i.e Schematic XL and Virtuoso GXL. I design the schematic of the architecture, first, then using the connectivity driven option, i generate...
    Posted to Custom IC Design (Forum) by nbtarun on Sat, Apr 3 2010
  • vdd not sensed in post-layout simulation

    Hi, I tried to do post layout simulation with extracted, symbolized inverter, however, I got the message during simualtion: Notice from spectre during topology check. Only one connection to node 'vdd!' I plot the output and confirmed that vdd is not applied to the internal transistors of the...
    Posted to Custom IC Design (Forum) by Malolo on Tue, Jan 12 2010
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