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Cadence

  • System Development – What To See At DAC 2010

    The EDA360 vision paper specifies key System Realization challenges. Embedded software development and verification are rapidly becoming the key increasing cost factors for the electronics industry. Integration and re-use are becoming critical for the success of any electronic company. In this blog,...
    Posted to System Design and Verification (Weblog) by Ran Avinun on Mon, Jun 7 2010
  • Filler Cells and Substrate Contacts in Virtuoso GXL

    Hi, I am using the student version of cadence tools at my Univ to auto place and route a custom design, using standard-cells. I am using the Custom IC tools suggested, i.e Schematic XL and Virtuoso GXL. I design the schematic of the architecture, first, then using the connectivity driven option, i generate...
    Posted to Custom IC Design (Forum) by nbtarun on Wed, Apr 7 2010
  • VIRTUOSO GXL Auto-Place & Route problems

    Hi, I am using the student version of cadence tools at my Univ to auto place and route a custom design, using standard-cells. I am using the Custom IC tools suggested, i.e Schematic XL and Virtuoso GXL. I design the schematic of the architecture, first, then using the connectivity driven option, i generate...
    Posted to Custom IC Design (Forum) by nbtarun on Sat, Apr 3 2010
  • How to suppress Spectre simulation for digital design?

    I am using Cadence 6.1.2 and NCSU_analog_parts library to do digital design. When I use spectre to simulate my circuit, it costs a long time (40 minutes at least) and a large file generated (more than 15MB). So I'd like to know how to suppress the simulation of Spectre? Because I think it may do...
    Posted to Custom IC Design (Forum) by Shengkui Gao on Thu, Feb 25 2010
  • vdd not sensed in post-layout simulation

    Hi, I tried to do post layout simulation with extracted, symbolized inverter, however, I got the message during simualtion: Notice from spectre during topology check. Only one connection to node 'vdd!' I plot the output and confirmed that vdd is not applied to the internal transistors of the...
    Posted to Custom IC Design (Forum) by Malolo on Tue, Jan 12 2010
  • Design Signoff Begins In Implementation

    As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs. For the majority of ASIC designs, signoff analysis includes...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Jan 6 2010
  • Display of schematic name and page number on the symbol

    Hi, I ported a design from 6.1 to 5.1.41. The symbols in 6.1 have the following statements which are supposed to display schematic name and page number when the symbol is instantiated. dsp('sheetIndex) dsp('page) In the ported design, after instantiation, I get the following, *Error* eval: undefined...
    Posted to Custom IC Design (Forum) by mk123 on Mon, Oct 19 2009
  • Re: Opening a 6.1 schematic in ver. 5.1.41

    Hi Lawrence, IC61x does open the existing design which has a cds.lib file so yes, what you say is true. However, the -cdslibpath option doesn't support cds.lib. There may be some env variable that can be changed to disable this. I tried creating my own lib.defs file and it seems to get to the next...
    Posted to Custom IC Design (Forum) by mk123 on Thu, Sep 17 2009
  • What is the syntax for creating pins withing SKILL

    I tried accessing the documentation, but it seems to be unavailable at my university this year. I was just wondering what the syntax for creating a pin is. I think it is dbCreatePin( ) but i don't know the parameters. Also is there a way to specify what material/metal the pin is created on?
    Posted to Custom IC Design (Forum) by JMCaJHU on Wed, Sep 16 2009
  • Opening a 6.1 schematic in ver. 5.1.41

    Hi, I have some schematics in the OA version 6.1 and I need to read them in the earlier Cadence version of 5.1.41. Is there a way to do this? Copying them and opening them didn't work as the way schematics are saved in 6.1 is different. Is there a script to do the conversion? Thanks, ~mk123
    Posted to Custom IC Design (Forum) by mk123 on Wed, Sep 16 2009
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