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Cadence

  • ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs

    The 32nm and 28nm process nodes, the most advanced nodes currently in production, pose formidable challenges in complexity, power management, variability, and manufacturability. A recent ARM TechCon paper authored by Cadence and Samsung described a methodology that can resolve those challenges. And it's...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 9 2011
  • ARM TechCon Highlights Roundup – Blogs, Videos, and More

    The recent ARM TechCon conference was a great success, and so much happened in 3 days there that it's very difficult to keep track of it all. Here's a "coverage roundup" that includes some pointers to blogs, articles, and videos that might help fill in anything you missed - or shed...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 3 2011
  • CDNLive! Silicon Valley 2012 Abstracts Due November 11th, 2011

    The Call for Papers for CDNLive! Silicon Valley 2012 is open now through Friday November 11th, 2012. CDNLive! is the Cadence users group conference. It provides an opportunity to present and listen to presentations from folks who use Cadence software to get their jobs done. Next year's conference...
    Posted to Digital Implementation (Weblog) by BobD on Wed, Nov 2 2011
  • ARM TechCon Address: High Stakes at Low Process Nodes

    The complexity of advanced-node IC designs is skyrocketing, and the demands on EDA tool development seem overwhelming - but innovation and deep collaboration will break through the challenges, according to Chi-Ping Hsu, senior vice president for R&D at the Silicon Realization group at Cadence. In...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 25 2011
  • environmental variables

    Hi, I set up the Cadence 16.3, it worked well and everything was ok. But after I ran the Visual Studio 2008 yesterday, the Cadence can't work now, the only message is "RPC server is not available ". Since yesterday it was the first time to run the VS 2008, it showed a window and took several...
    Posted to PCB Design (Forum) by Lionking on Fri, Oct 21 2011
  • NetList export from OrCAD to PADS or ALLEGRO

    Exploring more options to "communicate" through different CAD software. I'm now using Cadence Design Entry CIS to work on the schematic, and would like to export the netlist and import it into PADS and also ALLEGRO board design. For PADS, when I export the netlist through: Tools -->...
    Posted to PCB Design (Forum) by PCB EXPERT on Tue, Oct 18 2011
  • Hiring PCB Layout Designer

    We are looking for an experienced PCB Layout Engineer using Cadence and Allegro, Altium, for an immediate vacancy in Colorado. US citizens Qualifications: 5 years experience in PCB layout Understanding of industry design standards. Experience in working on multiple projects independently. Proficient...
    Posted to PCB Design (Forum) by GaileM on Thu, Oct 6 2011
  • Webinar: Easing the Pain of FPGA-Based Prototyping

    Nearly every digital system-on-chip, ASIC or ASSP is prototyped in FPGAs, most typically for pre-silicon software development and debugging. The problem is that it can take months to get the prototype up and running with a functionally equivalent design. But there are easier ways to develop FPGA-based...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 8 2011
  • GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow

    The design and manufacturing challenges of 20nm ICs are formidable, and will not be solved by loose collections of point tools. At the recent Global Technology Conference ( GTC ), Cadence presented its view of 20nm challenges and previewed a comprehensive 20nm design methodology that encompasses custom...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 7 2011
  • GTC Panel: Getting Best Use From Older IC Process Nodes

    Time for a mainstream revolution? That was the title of a lively panel discussion at the Global Technology Conference ( GTC ) Aug. 30. Panelists noted that there's still a lot of activity at 65nm and above. They discussed why this is true, whether mature nodes can be retrofitted with new capabilities...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 5 2011
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