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Cadence

EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs

Any new technology needs a driving force or "killer app," and 3D-ICs with through-silicon vias (TSVs) are no exception. By allowing a high-bandwidth, low-power connection between CPU and DRAM, the new JEDEC wide I/O mobile DRAM standard will be that driving force, according to Marc Greenberg...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 10 2012
spectreVerilog

Hello, I have being using spectreverilog tool to run some mixed signal sims. When I try to run pvt sims using ocean environment,the sims run fine but it looks for a license pair afresh as it is about to start the second PVT sim. It does not use the same set of spectre and verilog license it had acquired...

Posted to Custom IC Design (Forum) by uzzy on Tue, Apr 3 2012
High frequency quadrature VCO design with good phase noise

Hello everyone I am a newbie engineer starting my career in RF IC design and working on designing a high frequency VCO (38 GHz) with good phase noise characteristics. I am using Cadence IC6.1.5-64b.500 version and spectre simulator for the schemtic design and simulations. I have to do everything from...

Posted to Custom IC Design (Forum) by rohan kr on Thu, Mar 29 2012
CDNLive! Keynote – New Horizons for ARM Based SoCs

30 billion ARM-based chips have shipped over the last 20 years, but ARM isn't stopping there. ARM is looking beyond cell phones and mobile devices and pursuing new opportunities in the server, home entertainment, and automotive marketplaces, according to Tom Lantzsch (right), executive vice president...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 15 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?

Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 7 2012
EDA CEOs Speak Out: 3D-ICs, IP Integration, Low Power, and More

What's driving the EDA industry today and where is it headed in the near future? Some high-level answers to these questions came from the EDA Consortium (EDAC) annual CEO Forecast panel Feb. 29, 2012. EDA industry leaders shared their views about 3D-ICs, SoC integration, power management, industry...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 5 2012
DVCon User Panelists: Is Low Power Design Worth the Costs?

Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 29 2012
Free “Power” Lunch at DVCon Exposes Verification Challenges

A free lunch, a 50% off deal on a new verification book, and a chance to hear about real-world experiences in low-power verification -- it's all happening Tuesday Feb. 28 at the DVCon 2012 conference in San Jose, California. The Cadence-sponsored lunch, which runs from 12:30 pm to 2:00 pm, is titled...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 22 2012
Panelists: Bridging the Gap Between Analog and Digital Design

Analog and digital designers have lived in separate worlds for a long, long time. They use different methodologies and tools, and while digital design is heavily automated, analog design is not. But mixed-signal integration will force this gap to narrow, opening the door to new methodologies and better...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 1 2012
SPIE Papers Showcase DFM and Lithography R&D

Ten Cadence papers planned for the upcoming SPIE Advanced Lithography conference, set for Feb. 12-16 in San Jose, California, demonstrate recent R&D developments in both "design side" design for manufacturing (DFM) and the computational lithography that takes place during the manufacturing...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 26 2012

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Cadence

EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs

spectreVerilog

High frequency quadrature VCO design with good phase noise

CDNLive! Keynote – New Horizons for ARM Based SoCs

DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?

EDA CEOs Speak Out: 3D-ICs, IP Integration, Low Power, and More

DVCon User Panelists: Is Low Power Design Worth the Costs?

Free “Power” Lunch at DVCon Exposes Verification Challenges

Panelists: Bridging the Gap Between Analog and Digital Design

SPIE Papers Showcase DFM and Lithography R&D