	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

Cadence

DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

What will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 12 2012
DAC 2012: How Unified Coverage Interoperability Standard (UCIS) Will Ease IC Verification

Some significant news was announced at the Design Automation Conference June 4 - the official debut of the Unified Coverage Interoperability Standard ( UCIS 1.0 ) by the Accellera standards organization. Accellera hosted a June 6 lunch event at which Richard Ho (right), co-chair of the UCIS Committee...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 11 2012
DAC 2012: Connecting Emulation to the Real World of Wireless Interfaces

This is certainly the most connected DAC I have been to so far. Tweets and connections everywhere, blogging is happening left and right. A lot of the attendees hold their wireless devices in their hands. It is rewarding that we are part of enabling all that. Living proof of that came today from our System...

Posted to System Design and Verification (Weblog) by fschirrmeister on Tue, Jun 5 2012
DAC 2012: EDA Industry Celebrates 10 Years of OpenAccess

The OpenAccess standard, which includes a common data model, API and reference database, has been one of the most successful and impactful standards in EDA history. Those who imagined, created, and continue to maintain and improve OpenAccess got some long overdue recognition June 4 at a Silicon Integration...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 4 2012
TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem

Perhaps the most challenging question about 3D-IC design is what gets done when, by which kind of provider. With its recently introduced chip-on-wafer-on-substrate ( CoWoS ) process, TSMC has taken a step towards clarifying what the 3D-IC ecosystem might look like. And Cadence helped refine the methodology...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 4 2012
DAC 2012 Gary Smith EDA Kickoff: EDA and ESL Growth and Four Different Software Virtual Prototypes

DAC 2012 kicked off yesterday with the annual DAC Reception followed by Gary Smith's keynote detailing challenges in EDA. For system-level design there was some really good news, but also some interesting detailed refinement on how much effort virtual prototyping for enablement of software development...

Posted to System Design and Verification (Weblog) by fschirrmeister on Mon, Jun 4 2012
DAC 2012: Handling a Double Paradigm Shift for Embedded Software Development

Change is hard. And we in product marketing for development tools are trying to cause change and find out if and how users are adopting new methodologies and tools. A little over a year ago, in the spirit of fellow Blogger Steve Leibson's law, that "it takes 10 years for any disruptive technology...

Posted to System Design and Verification (Weblog) by fschirrmeister on Mon, Jun 4 2012
Cadence EDA360 Theater – Customers, Partners Speak Out at DAC 2012

Sometimes it's best to let other people do the talking. That's the approach Cadence has taken this year at the Design Automation Conference ( DAC 2012 ) at the EDA360 Theater at the Cadence booth (#1930). This theater will feature three days of presentations by customers and partners in an informal...

Posted to Industry Insights (Weblog) by rgoering on Tue, May 29 2012
How to add a company logo or a marking seregraphy with "Allegro PCB Design"

Hi, how to add a company logo, a picture, or a marking seregraphy in PCB board with "Allegro PCB Design", see exemple in attached image: Best regards, Haithem.

Posted to PCB Design (Forum) by HaithemEmbedde on Mon, May 28 2012
Re: cadence encounter flow

thanks for the response sir.but i am unable to open the link even after entering the host id of the system. can u please tell me about the post layout simulation of the design in cadence tool?I did not get the steps to do that.I have done with DRC and LVS of the circuit.

Posted to Digital Implementation (Forum) by shakun on Sun, May 27 2012

Page 13 of 22 (216 items) « First ... < Previous 11 12 13 14 15 Next > ... Last »

Popular Tags

Email

Share

Subscribe

Contact Us

Cadence

DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

DAC 2012: How Unified Coverage Interoperability Standard (UCIS) Will Ease IC Verification

DAC 2012: Connecting Emulation to the Real World of Wireless Interfaces

DAC 2012: EDA Industry Celebrates 10 Years of OpenAccess

TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem

DAC 2012 Gary Smith EDA Kickoff: EDA and ESL Growth and Four Different Software Virtual Prototypes

DAC 2012: Handling a Double Paradigm Shift for Embedded Software Development

Cadence EDA360 Theater – Customers, Partners Speak Out at DAC 2012

How to add a company logo or a marking seregraphy with "Allegro PCB Design"

Re: cadence encounter flow