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Electronic System Level (ESL) Design Gets a Pragmatic Look at EDPS Workshop
Presentations at the Electronic Design Process Symposium (EDPS) April 18, 2013 gave a realistic look at the promises and limitations of electronic system level (ESL) design. Speakers noted that ESL tools are used for the lower levels of the software stack, but typically not for applications development...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 21 2013
DVCon 2013 Expert Panel: How to Succeed with Verification Planning
While formalized methodologies now exist for many aspects of functional verification, verification planning is still largely an ad-hoc process. Yet verification planning is becoming increasingly important as chips get more complex. At the recent DVCon 2013 conference, a panel of verification experts...
Posted to
Industry Insights
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by
rgoering
on Tue, Mar 5 2013
DVCon 2013 Lunch Panel: Best Practices in Verification Planning
While standardized methodologies guide many other aspects of functional verification, planning the verification process is as much an art as a science. How can you know if you're following "best practices" in verification planning? One way to find out is to attend a Cadence sponsored luncheon...
Posted to
Industry Insights
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rgoering
on Thu, Feb 14 2013
System Design 2012 – Real Users Achieving Real Results!
This morning the final success story my team has been working on for this year went live. Texas Instruments reports on how they achieved greater than 90% accurate correlation between an architectural power estimation and actual silicon! This deserves its own blog early next year, but meanwhile, it has...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Fri, Dec 21 2012
Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design
Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level synthesis and virtual prototyping are seeing adoption and showing results in more and more production environments...
Posted to
Industry Insights
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rgoering
on Mon, Oct 8 2012
DAC2012: Xilinx Zynq-7000 - From RTL to Success with Emulation
It is nice to see when visions get closer to reality. When Cadence announced its vision for the System Development Suite back in 2011, offering a continuum of engines from virtual prototyping through RTL simulation, acceleration and emulation all the way to FPGA based prototyping seemed aggressive. Or...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Mon, Jul 2 2012
DAC 2012: The Top Seven Reasons for using FPGA Based Prototyping
John Blyler, Editorial Director at Extension Media , presented in our EDA360 Theatre at DAC 2012 about "ASIC/ASSP Prototyping with FGPAs" and provided an update on his annual survey on this topic. The current 2012 survey is actually currently ongoing and you can still participate here . FPGA...
Posted to
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fschirrmeister
on Thu, Jun 28 2012
DAC 2012: Enabling the Programming of an Extensible Processing Platform
We at Cadence have been writing about the virtual prototype associated with the Xilinx Zynq-7000 Extensible Processing Platform (EPP) quite a bit. At the recent Design Automation Conference (DAC) it was our pleasure to welcome Dave Beal from Xilinx in the EDA360 Theatre to talk about Zynq, its programming...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Tue, Jun 26 2012
High-Level Synthesis Users: Productivity Gains Beckon, But Learning Curve Comes First
SystemC-based high-level synthesis (HLS) tools have greatly improved in recent years and are undergoing adoption by many large semiconductor companies. But to get high productivity out of HLS, current RTL designers will first face a learning curve, according to panelists at the recent Design Automation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 25 2012
DAC 2012: Users Cite Experiences With Hardware/Software Co-Development
Hardware/software co-development tools such as virtual prototyping, emulation, and FPGA-based prototyping are in use today and are making a difference. That was the message behind a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 5, where two users described their experiences...
Posted to
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rgoering
on Sun, Jun 17 2012
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