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Cadence,Virtuoso

  • Help with complete understanding of "vsin" source in Cadence

    Hi. I kind of thoroughly Googled before posting this question for seeking help from you guys! The "vsin" source (in analogLib) of Cadence has many parameters: i) AC magnitude, AC phase, DC voltage ii) Offset voltage, Amplitude, Frequency,... Question 1: Internet resources are indicating that...
    Posted to Custom IC Design (Forum) by jdp721 on Sun, May 11 2014
  • Top Ten Cadence Community Blog Posts of 2013

    In 2013, Cadence Community bloggers published over 375 posts in categories including Industry Insights, Functional Verification, Fuller View, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation. Below is a listing, in order...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Dec 15 2013
  • Q&A: MEMS Begin to Enter the Semiconductor Design Mainstream

    Micro-electrical mechanical systems (MEMS) have been a niche technology for many years, but a new generation of MEMS ICs is emerging, according to Mike Jamiolkowski, CEO of Cadence partner and MEMS tool provider Coventor. Barriers to the use of MEMS technology, such as the need for PhD-level experts...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 11 2013
  • ICCAD 2013: The New Electrically Aware Design Paradigm

    SAN JOSE, Calf.--Pop quiz: What percentage of verification time do design teams spend on re-iterating their layout design after checking electrical parameters? If you said 30-40 percent, move to the head of the class. And given the ceaseless increase in design complexity, you'd expect that percentage...
    Posted to The Fuller View (Weblog) by Brian Fuller on Tue, Nov 26 2013
  • Re: Writing out .lib & lef from virtuoso

    Hello Andrew, Thanks for the help.. The issue with lef is that once I export lef from virtuoso and read this to encounter,its not recognised by encounter as a macro. Can we use the lef generated by File->Export->LEF in virtuoso directly to encounter ? Or anything else need to be done for generating...
    Posted to Custom IC Design (Forum) by Shameel on Mon, Oct 7 2013
  • Cadence‚Äôs Annual Mixed-Signal Summit 2013: A Mind Meld of Mixed-Signal Design Community

    If you're a fan of the Star Trek series (my six-year-old son and I watch it together faithfully!), you know the Vulcan Mind Meld. (If you're not a Trekkie, the mind-meld is a process of transferring one's knowledge to another person instantly). Mixed-Signal Technology Summit , Oct. 10 at...
    Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Mon, Oct 7 2013
  • Writing out .lib & lef from virtuoso

    Hi All How can I write out .lib file of a digital module designed in virtuoso ? Also If I want to import this module as a digital block to encounter, how can I make it as a macro/cell ? How to take care of this while writing out lef from virtuoso ? Thanks Shameel
    Posted to Custom IC Design (Forum) by Shameel on Sun, Oct 6 2013
  • Virtuoso 6.1.5 to encounter

    Hi All, I have implemented a digital block in transistor level using virtuoso 6.1.5 . I want to do the IO placement for it. The IO library that I had has the following files in it. ===================================================== --> <folderPath>/BackEnd/ * LEF P & R model (in <folderPath>...
    Posted to Digital Implementation (Forum) by Shameel on Wed, Sep 25 2013
  • Virtuoso 6.1.5 to encounter

    Hi All, I have implemented a digital block in transistor level using virtuoso 6.1.5 . I want to do the IO placement for it. The IO library that I had has the following files in it. ===================================================== --> <folderPath>/BackEnd/ * LEF P & R model (in <folderPath>...
    Posted to Digital Implementation (Forum) by Shameel on Wed, Sep 25 2013
  • TSMC 3D-IC Reference Flow Supports 3D Die Stacking

    An important milestone for any new semiconductor technology is the availability of a foundry EDA reference flow. Such a milestone occurred last week (Sept. 18, 2013) as Cadence and TSMC delivered the latest Cadence 3D-IC reference flow for true 3D die stacking (right). While there has been considerable...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 24 2013
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