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Cadence,QRC,test chip

  • ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

    All 20nm test chips are learning experiences, and a recent tapeout of a 20nm Cortex-M0 test chip by ARM engineers was no exception. Completed in June 2012, the test chip design used a Cadence digital implementation flow. The story of the test chip is told in a new guest partner blog (I'm the "guest"...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Nov 27 2012
  • ARM TechCon: Inside Story of a 14nm FinFET Tapeout

    The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 31 2012
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