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DVCon 2013 Expert Panel: How to Succeed with Verification Planning
While formalized methodologies now exist for many aspects of functional verification, verification planning is still largely an ad-hoc process. Yet verification planning is becoming increasingly important as chips get more complex. At the recent DVCon 2013 conference, a panel of verification experts...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 5 2013
Securing Invisible Things … or “Why Denial Works!”
The opening keynote of the Embedded World conference in Germany left me with chills. No, it was not a grand theatrical performance letting me crave for more. It simply scared the bejevies out of me with respect to the safety and security of embedded devices, some of which I use each day. Luckily -- as...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Wed, Feb 27 2013
DVCon 2013 Lunch Panel: Best Practices in Verification Planning
While standardized methodologies guide many other aspects of functional verification, planning the verification process is as much an art as a science. How can you know if you're following "best practices" in verification planning? One way to find out is to attend a Cadence sponsored luncheon...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 14 2013
DVCon 2013 Preview – Learn from Other Design and Verification Engineers
The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 24 2013
Free UVM Tutorial Boosts IC Functional Verification Skills
Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day tutorial, titled " UVM: Ready, Set, Deploy! " is available through the Accellera Systems...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 12 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?
Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 7 2012
DVCon User Panelists: Is Low Power Design Worth the Costs?
Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 29 2012
Free “Power” Lunch at DVCon Exposes Verification Challenges
A free lunch, a 50% off deal on a new verification book, and a chance to hear about real-world experiences in low-power verification -- it's all happening Tuesday Feb. 28 at the DVCon 2012 conference in San Jose, California. The Cadence-sponsored lunch, which runs from 12:30 pm to 2:00 pm, is titled...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 22 2012
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