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Cadence,ARM

EDA CEOs Reveal Thoughts About Present and Future of EDA Industry

At an EDA Consortium ( EDAC ) panel discussion March 14, 2013, top executives from Cadence, Mentor, Synopsys, ARM, and EDA startup Nimbus shared their views about a range of business and technology issues facing the EDA industry. Panelists engaged in lively discussions about topics including consolidation...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 18 2013
Samsung CDNLive Keynote: Innovation and Challenges in the Post-PC Era

We are living through a "disruptive" transition in which a PC-driven market is giving way to a mobile-driven market, according to Young Sohn, president and chief strategy officer for device solutions at Samsung Electronics. In a keynote speech March 12, 2013 at the CDNLive Silicon Valley conference...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 13 2013
System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet

Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December last year -- 15 years in -- I summarized a great...

Posted to System Design and Verification (Weblog) by fschirrmeister on Fri, Mar 8 2013
Video: What the Newly Approved IEEE 1801-2013 Low Power Format (UPF 2.1) Includes

The IEEE RevCom (Review Committee) approved a new version of the IEEE 1801 low power format, also known as the Unified Power Format (UPF), March 5. The new version is IEEE 1801-2013 or UPF 2.1. It's a significant step towards "methodology convergence" with the Common Power Format (CPF)...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 6 2013
Securing Invisible Things … or “Why Denial Works!”

The opening keynote of the Embedded World conference in Germany left me with chills. No, it was not a grand theatrical performance letting me crave for more. It simply scared the bejevies out of me with respect to the safety and security of embedded devices, some of which I use each day. Luckily -- as...

Posted to System Design and Verification (Weblog) by fschirrmeister on Wed, Feb 27 2013
10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

10nm and 14nm FinFET design will have a lot of challenges, but collaboration among semiconductor ecosystem partners is finding solutions, according to a presentation given at the Common Platform Technology Forum Feb. 5, 2013. The presentation was given by Vassilios Gerousis (right), distinguished engineer...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 12 2013
Common Platform Forum Keynotes: 14nm FinFETs and Beyond

How far can we continue to scale semiconductors? 14nm FinFET technology is the next major move, but that's far from the end of the story, according to keynote speakers at the Common Platform Technology Forum in Santa Clara, California Feb. 5, 2013. The keynotes, still available for on-line viewing...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 6 2013
BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor

A 3D multi-gate transistor called the FinFET promises tremendous power and performance advantages at 16nm and 14nm process nodes (and was adopted at 22nm by Intel) -- but nobody can use FinFETs without an accurate compact model. Fortunately, the BSIM-CMG model available from the University of California...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 21 2013
Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 7 2013
System Design 2012 – Real Users Achieving Real Results!

This morning the final success story my team has been working on for this year went live. Texas Instruments reports on how they achieved greater than 90% accurate correlation between an architectural power estimation and actual silicon! This deserves its own blog early next year, but meanwhile, it has...

Posted to System Design and Verification (Weblog) by fschirrmeister on Fri, Dec 21 2012

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Cadence,ARM

EDA CEOs Reveal Thoughts About Present and Future of EDA Industry

Samsung CDNLive Keynote: Innovation and Challenges in the Post-PC Era

System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet

Video: What the Newly Approved IEEE 1801-2013 Low Power Format (UPF 2.1) Includes

Securing Invisible Things … or “Why Denial Works!”

10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

Common Platform Forum Keynotes: 14nm FinFETs and Beyond

BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor

Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

System Design 2012 – Real Users Achieving Real Results!