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Cadence 6.1

  • Misalignment of schematic while porting

    When I am porting schematic library from x foundry to y foundry (for now assume all other instance properties like width length etc are same), there is misalignment so net connectivity is lost. For example if i have nmos in x foundry on converting to Y foundry it is getting shifted and rotated. So what...
    Posted to Custom IC SKILL (Forum) by garry01 on Wed, May 21 2014
  • Moving over to 6.1.4

    Hi Cadence Community I am having a bit of a problem transitioning existing layout designs from Cadence’s Virtuoso 5.10.4 to Virtuoso 6.1.4. Using the Conversion Tool Box feature CDB to OpenAccess Translator that is provided. The design transition over to 6.1.4 is relatively smooth, lvs checks are...
    Posted to Custom IC SKILL (Forum) by flintae32 on Tue, Nov 19 2013
  • Memory issues with ocean script (Monte-Carlo+Parametric analysis)

    Hi all, (sorry for this loooong first post :) ) - I need to do a Monte-Carlo simulation (Virtuoso 6.1.5) for a RF circuit with N runs for different combinaisons of parameters (voltages V1 to V4) - For each of the 256 combinaisons I want to run a Monte-Carlo to evaluate 4 different parameters (like gain...
    Posted to Custom IC SKILL (Forum) by Martin A on Tue, Jul 23 2013
  • Reading Inherited Net names from the current cellview

    Hi, I am having difficulty reading the inherited net names of a schematic. I have a schematic with inherited connections for VDD!, VSS!, VNW! and VPW!. At the upper layer of hierarchy I have set the net expression properties to ensure these nets are connected to avdd, gnd, vsubn, vsubp. Starting from...
    Posted to Custom IC SKILL (Forum) by NiallDuncan on Wed, Jun 26 2013
  • inner workings of Virtuoso Copy command

    Greetings forum Does the Copy command under virtuoso place db objects into a "paste" buffer that is still maintained after the copy command is terminated which could be accessed with a SKILL command some amount of time later ? Is the buffer erased and filled with a new object once the copy...
    Posted to Custom IC SKILL (Forum) by Malcolmw on Thu, Jun 20 2013
  • *Error* fprintf/sprintf: illegal format spec. - " $monitor(\"Time: %t, Control Variable %f\\n\",$time,Ctrl_1_);\n"

    Hello, Try to Create a Cadence view from the verilog file. Here is my section of the skill that it is having problem with. If somebody has a easier way to create a Cadence view from a file let me know as well. I know what the problem here is but do not know the solution yet. if((ddGetObj(libName cellName...
    Posted to Custom IC SKILL (Forum) by skillseeker on Mon, May 20 2013
  • hiSaveAsViewFile() trouble in Virtuoso v6

    I have a script (http://www.cadence.com/Community/forums/p/24288/1317148.aspx#1317148) that will save the design tree file to a shell to run a shell script on, working in Virtuoso v5, but is breaking in Virtuoso v6 on the command hiSaveAsViewFile. The Save File As form looks quite different in v6, but...
    Posted to Custom IC SKILL (Forum) by jaleco on Tue, Feb 5 2013
  • Turn off Enter Forms in v6

    Does anyone know how to turn off the visibility of the Enter Forms for common functions in Virtuoso v6? For example, the stretch, move, copy, etc commands under the Edit menu, whether called by the pulldown or by bindkey, popup an Enter Form that I only saw in v5 by using the F3 key. Is there a setting...
    Posted to Custom IC SKILL (Forum) by jaleco on Sat, Jan 26 2013
  • Skill code to apply instance orientation to a cordinate

    Hi, I'm looking to extract label cordinates of an instance based on how the instance is placed, i.e, after factoring in the orientation of the instance. Has anyone written code like this? For eg. x:y = 10:20 would become -10:20 after MY, 20:10 after MYR90 Thanks, Shaju
    Posted to Custom IC SKILL (Forum) by shajujan on Tue, Jan 15 2013
  • BindKey - Error in IC6

    Hi experts, I'm facing some issue with pre-loaded bindkeys after virtuoso upgraded from IC5.1.X to IC6.1.X. The Error is related to the skill command "leSetAllLayerValid" (complaining cannot get current techfile in the LSW"). I believe this is due to the diff program loading sequence...
    Posted to Custom IC SKILL (Forum) by Peter123 on Thu, Dec 13 2012
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