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Cadence 16.5,pcb editor

  • PCB Editor can't load symbols (create netlist warnings)

    Hi, When I want to create Netlist I see some warning messages in OrCAD Capture which makes PCB Editor unable to load symbols. I have used DB doctor so many times - according to message hint - with all instructions given in below post. But nothing changes: http://www.cadence.com/Community/forums/p/20129...
    Posted to PCB Design (Forum) by Hossein1357 on Tue, Jun 17 2014
  • homogenous symbols

    Hi, I am using Homogenous -'parts per package' symbol on my design. i get a netlisting error if i dont connect the power pins present on all the parts. ( for eg. for a HEX inverter IC with 6 parts, the power (#14) & GND (#7) pins are present on all the parts. ) is there a way to avoid connecting...
    Posted to PCB Design (Forum) by marysmita on Thu, Jul 4 2013
  • 16.5 New footprint from Package Designer to PCB Editor?

    Hello, I am a new 16.5 user. I designed some footprints in package designer as per the tutorials. I saved them in a folder as .psm and .dra parts. However when I go to create a netlist in Capture, or even to simply manually place the parts in PCB Editor neither I nor the software can find them. In PCB...
    Posted to PCB Design (Forum) by Grue42 on Tue, Oct 16 2012
  • Component Browser: Footprint is not defined for a part.

    Hi, After creating part/symbol in Part Developer using PCB Librarian, I tried to test the part in DE HDL through PCB Librarian. When I placed the part, Component Browser shows an error, Footprint is not defined for a part. What might be the cause of this error? But when I tried to export the schematic...
    Posted to PCB Design (Forum) by maberu on Thu, Jul 19 2012
  • Ground Plane split in PCB editor - Isolated ground plane creation

    I am new to PCB design. Designing a PCB which has isolated grounds. To create splitted ground I follow this procedure. 1. Run add line. 2. In the Options tab, choose ANTI-ETCH class and the subclass where you want the split plane. 3. In the Options tab, use the line width setting to control the clearance...
    Posted to PCB Design (Forum) by PCBdesigner100 on Fri, Jul 13 2012
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