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Cadence 16.5

  • Converting .max file to .brd file

    Hi everyone, i just converted my .max fles (10.5 version) to .brd files to work on the 16.5 version. After i converted my MAX file to BRD file thru orcad layout translator in 16.5 suite, some shapes,connections and vias are missed in that. And some Clines were changed thier nets. how can i get or convert...
    Posted to PCB Design (Forum) by shreeja on Fri, Sep 12 2014
  • Re: Allegro Symbol creation Error

    Hi, Thank you very much for your answer. After creating this post, I remembered your comments on a similar problem that you had commented last week. So I run DBDoctor and could fix the issue. Unfortunately, I couldn't delete my post.So sorry for any inconvenience. By the way, How can I delete my...
    Posted to PCB Design (Forum) by Hossein1357 on Mon, Jul 7 2014
  • PCB Editor can't load symbols (create netlist warnings)

    Hi, When I want to create Netlist I see some warning messages in OrCAD Capture which makes PCB Editor unable to load symbols. I have used DB doctor so many times - according to message hint - with all instructions given in below post. But nothing changes: http://www.cadence.com/Community/forums/p/20129...
    Posted to PCB Design (Forum) by Hossein1357 on Tue, Jun 17 2014
  • Different axes orientation in symbol and PCB Editors

    Hi all, I am designing a symbol for 0402 components. I define (28mil,22mil) as (Width,Height) sizes in pad designer and every thing looks correct in my package Designer - as is seen in below link: https://drive.google.com/file/d/0BzS3_lT7y4tEaGFwREJsX0Z2OTQ/edit?usp=sharing Unfortunately, as far as I...
    Posted to PCB Design (Forum) by Hossein1357 on Tue, Jun 17 2014
  • Help with editing Schematic Description

    I am trying to create scheatic using Allegro Design Entry HDL (Version 16.5). I am learning this software since 2-3 days and I need help on how to edit the schematic description like <DRAWING_TITLE_HEADER>, <PRODUCT>, etc. (Please find corresponding image attached) I tried going to Tools>Options>Custom...
    Posted to PCB Design (Forum) by abhikuvar on Fri, Apr 18 2014
  • Multi-site design HDL reference designators

    Hi there, HDL DE newbie here. We're doing a multi-site design schematic entry with part name ref des as, say, 1R1; where 1=site num and R1= is resistor 1. I would like to know how to copy the component or the whole site schematic wherein the parts ref des will be updated to it's respective site...
    Posted to PCB Design (Forum) by comet on Sun, Feb 9 2014
  • Why the same net via and shape can not connect togeter?

    I have met a problem when use 16.5 in divide power layer, the same net with the dynamic shape and via cannot connect together. just like pic as follow or link. The via avoid the shape. And I want to know how to solve it, thanks a lot! http://xiangce.baidu.com/picture/detail/8f2f80782f2eeecf44752e05fa10543a59b5931c
    Posted to PCB Design (Forum) by Sunner on Fri, Nov 22 2013
  • DE HDL v16.5 -- Bus Tap

    DE HDL noob here... why is that i couldn't place a wire tap between a bus and symbol pin?... prompted with a warning "Could not find body for CTAP". TIA!
    Posted to PCB Design (Forum) by comet on Wed, Oct 2 2013
  • Ignore a component in netlist

    Hi, Im using 16.5 version of cadence. recently i developped a schematic. after doing a netlist generation, the session log showed me that "the part 14 does n't contains any pins pls ignore the components in netlist". i looked everywhere in my schematic there is no part 14 and even im not...
    Posted to PCB Design (Forum) by shreeja on Thu, Sep 5 2013
  • how to create a pspice own parts

    hello everyone, can someone help me that how to create a parts which has to be used for simulating purpose. even i tried in model editor, which is asking a .lib format file. i searched everywhere in my drives im not having that type of format. how to create or convert by the use of .olb files. please...
    Posted to PCB Design (Forum) by shreeja on Wed, Aug 21 2013
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