Home > Community > Tags > Cadence 16.5/DRC rules
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Cadence 16.5,DRC rules

  • DRC T error

    I have a DRC error saying that T's allowed is set to pads and vias only. Where do I change this to allow T's anywhere?
    Posted to PCB Design (Forum) by tmd63 on Fri, Apr 19 2013
Page 1 of 1 (1 items)