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Cadence 16.5,Allegro PCB Editor

  • Why the same net via and shape can not connect togeter?

    I have met a problem when use 16.5 in divide power layer, the same net with the dynamic shape and via cannot connect together. just like pic as follow or link. The via avoid the shape. And I want to know how to solve it, thanks a lot! http://xiangce.baidu.com/picture/detail/8f2f80782f2eeecf44752e05fa10543a59b5931c
    Posted to PCB Design (Forum) by Sunner on Fri, Nov 22 2013
  • Missing Drill symbols on the board

    Hello, I have a situation. I have prepared the PCB layout with no issues but the point i stuck on is, i dont see the drill symbols on the prepared board.. e.g I have a through hole pin connectors on my board, i can see the pad stacks, thermal relief and all other things which are there in the footprint...
    Posted to PCB Design (Forum) by raul5565 on Tue, May 14 2013
  • DRC T error

    I have a DRC error saying that T's allowed is set to pads and vias only. Where do I change this to allow T's anywhere?
    Posted to PCB Design (Forum) by tmd63 on Fri, Apr 19 2013
  • Design Entry HDL Training

    Hi there! Is there any training offering for Design Entry HDL here in Philippines? Please let me know. Thanks.
    Posted to PCB Design (Forum) by comet on Thu, Jan 24 2013
  • 16.5 New footprint from Package Designer to PCB Editor?

    Hello, I am a new 16.5 user. I designed some footprints in package designer as per the tutorials. I saved them in a folder as .psm and .dra parts. However when I go to create a netlist in Capture, or even to simply manually place the parts in PCB Editor neither I nor the software can find them. In PCB...
    Posted to PCB Design (Forum) by Grue42 on Tue, Oct 16 2012
  • Setup Test Sizes - template

    I understant how to change test characteristics using Setup>Design Parameters>Text>Setup Text Sizes. Is there a way to import and Export the settings that are entered into the texts sizes table?
    Posted to PCB Design (Forum) by crunch on Fri, Sep 7 2012
  • Allegro PCB Designer : Interlayer Spacing ?

    Hi, I'm currently working with Cadence 16.5 and I would like to add an interlayer spacing constraint for two adjacent layers, in order to prevent interlayer crosstalk between differential pairs. I spent some hours looking for a solution, and I found this post : http://www.cadence.com/Community/forums...
    Posted to PCB Design (Forum) by mxlecanu on Thu, Jul 26 2012
  • Component Browser: Footprint is not defined for a part.

    Hi, After creating part/symbol in Part Developer using PCB Librarian, I tried to test the part in DE HDL through PCB Librarian. When I placed the part, Component Browser shows an error, Footprint is not defined for a part. What might be the cause of this error? But when I tried to export the schematic...
    Posted to PCB Design (Forum) by maberu on Thu, Jul 19 2012
  • Ground Plane split in PCB editor - Isolated ground plane creation

    I am new to PCB design. Designing a PCB which has isolated grounds. To create splitted ground I follow this procedure. 1. Run add line. 2. In the Options tab, choose ANTI-ETCH class and the subclass where you want the split plane. 3. In the Options tab, use the line width setting to control the clearance...
    Posted to PCB Design (Forum) by PCBdesigner100 on Fri, Jul 13 2012
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