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Cadence 16.5,16.5

  • Help with editing Schematic Description

    I am trying to create scheatic using Allegro Design Entry HDL (Version 16.5). I am learning this software since 2-3 days and I need help on how to edit the schematic description like <DRAWING_TITLE_HEADER>, <PRODUCT>, etc. (Please find corresponding image attached) I tried going to Tools>Options>Custom...
    Posted to PCB Design (Forum) by abhikuvar on Fri, Apr 18 2014
  • Multi-site design HDL reference designators

    Hi there, HDL DE newbie here. We're doing a multi-site design schematic entry with part name ref des as, say, 1R1; where 1=site num and R1= is resistor 1. I would like to know how to copy the component or the whole site schematic wherein the parts ref des will be updated to it's respective site...
    Posted to PCB Design (Forum) by comet on Sun, Feb 9 2014
  • Why the same net via and shape can not connect togeter?

    I have met a problem when use 16.5 in divide power layer, the same net with the dynamic shape and via cannot connect together. just like pic as follow or link. The via avoid the shape. And I want to know how to solve it, thanks a lot! http://xiangce.baidu.com/picture/detail/8f2f80782f2eeecf44752e05fa10543a59b5931c
    Posted to PCB Design (Forum) by Sunner on Fri, Nov 22 2013
  • DRC T error

    I have a DRC error saying that T's allowed is set to pads and vias only. Where do I change this to allow T's anywhere?
    Posted to PCB Design (Forum) by tmd63 on Fri, Apr 19 2013
  • Generating a BOM

    Has anyone generated a BOM from OrCAD like this? I use version 16.5 here. I get close with variant report but I am not there yet. Any suggestions would be very welcome. Quantity#Part Reference#PART_NUMBER#VARIANT#LAYER 1#PCB1#P00001-1#1,2,#t 1#C1#P00002-0212#1,2,#t 1#C2#P00006-102#1,2,#b 1#C3#P00007...
    Posted to PCB Design (Forum) by Garry on Tue, Apr 16 2013
  • Design Entry HDL Training

    Hi there! Is there any training offering for Design Entry HDL here in Philippines? Please let me know. Thanks.
    Posted to PCB Design (Forum) by comet on Thu, Jan 24 2013
  • 16.5 New footprint from Package Designer to PCB Editor?

    Hello, I am a new 16.5 user. I designed some footprints in package designer as per the tutorials. I saved them in a folder as .psm and .dra parts. However when I go to create a netlist in Capture, or even to simply manually place the parts in PCB Editor neither I nor the software can find them. In PCB...
    Posted to PCB Design (Forum) by Grue42 on Tue, Oct 16 2012
  • FPGA pin swap

    Here is the problem. I have schematic where I have 484 pin FPGA. It is drawn in Allegro Cadance schematic capturing. So, to tailor it to my need i swapped pins around on FPGA (schematic reuse). Next what happen is we needed to go to same part but different part number for FPGA. So, after i used modify...
    Posted to PCB Design (Forum) by Alex71 on Tue, Oct 9 2012
  • Setup Test Sizes - template

    I understant how to change test characteristics using Setup>Design Parameters>Text>Setup Text Sizes. Is there a way to import and Export the settings that are entered into the texts sizes table?
    Posted to PCB Design (Forum) by crunch on Fri, Sep 7 2012
  • Allegro PCB Designer : Interlayer Spacing ?

    Hi, I'm currently working with Cadence 16.5 and I would like to add an interlayer spacing constraint for two adjacent layers, in order to prevent interlayer crosstalk between differential pairs. I spent some hours looking for a solution, and I found this post : http://www.cadence.com/Community/forums...
    Posted to PCB Design (Forum) by mxlecanu on Thu, Jul 26 2012
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