Home > Community > Tags > Cadence 16.3
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Cadence 16.3

  • Design Entry CIS 16.3 Trouble Starting

    My computer was recently re-loaded with Windows 7 64-bit. I installed Design Entry 16.3 and had been working with it for a week or two. A couple of days ago I tried to start Design Entry from the start menu. I get the normal splash screen, but then the main window never appears. "Allegro Design...
    Posted to PCB Design (Forum) by Kirilian on Thu, Feb 2 2012
  • rpc server not available

    Hello, all. I have installed the Cadence 16.3. and it worked well. Several days later I launched Visual studio 2008 and came the problem. In capture, I want to put two VSTIM in SOURCSTM library. When I use the option " edit-pspice stimulus ", it gave me the message that "Only one instance...
    Posted to PCB Design (Forum) by Lionking on Wed, Oct 26 2011
  • Re: Signal Name - Global Rename in Capture

    You can find and replace text using the "Find And Replace Text" application in the TCL Dashboard. You can launch the TCL application dashboard by going to the menu "Accessories -> Cadence TCL/Tk Utiltities -> Utilities" "Find And Replace Text" application supports...
    Posted to PCB Design (Forum) by hmkr on Tue, Sep 13 2011
  • [HELP] Allegro PCB file lost

    Hi guys, I just met a big problem with Allegro 16.2. I have layout all the pins on my 4-layer pcb. But I found one component had a wrong pin net name, so I updated it in Capture. After then, I re-open the .brd file and want to update the pcb, at this time, Allegro PCB design GXL pop up a warning! "WARNING...
    Posted to PCB Design (Forum) by cshinyc on Sun, Sep 11 2011
  • Warnings Creating a Netlist

    Hello i'm trying to make a PCB desing using the Cadence OrCAD Release 16.3, when i finish doing my schematic on Capture, and i try to create a netlist, there is a warning message that refers me to the "netrev.lst" file, i open it and there are this 2 errors: #1 WARNING(SPMHNI-192): Device...
    Posted to PCB Design (Forum) by EaCmBoThOm on Tue, Aug 23 2011
  • how to update a footprint in Allegro PCB Editor 16.3

    Hi, I am now using Allegro PCB editor to layout my circuit and got a problem: During the layout process I modified the footprint (.psm file) of one IC, but I don't know how to update it in my .brd file. I tried ECO in OrCAD capture but it didn't work. In PCB editor, I also tried several methods...
    Posted to PCB Design (Forum) by hopking on Sun, Jul 17 2011
  • How to have different pins named identically in part developer ?

    Hello everybody. I am working on Cadence 16.3 with capacitors which have a dip8 footprint. I want to create a symbol with part developer which has only two connections (pin 1 and pin 2). But, I do not manage to map a logical pin twice. And if I map my two pins as global pins (pin 1 mapped to 1,2,3,4...
    Posted to PCB Design (Forum) by romaric on Mon, May 23 2011
  • hierarchical designs in Cadence 16.3

    Hello everybody. I am facing a new problem. I have done a hierarchical design using a block and when I export the design and then back annotate, all the part of the block appear on the placement list in Allegro but ther isn't any annotation on the schematics.All symbols have their location defined...
    Posted to PCB Design (Forum) by romaric on Wed, May 18 2011
Page 2 of 2 (18 items) < Previous 1 2