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Amazon’s New Kindles: More Steps Toward the Paperback Computer
While I understand that a new Kindle Fire at $199 MRSP is significantly more than a dime novel, I assert that today's launch of the new Amazon tablets takes us one step closer to the "paperback computer" becoming a reality. Here the term paperback computer isn't just a clever play on...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Wed, Sep 28 2011
Image Gallery: Cadence-Denali Party at DAC 2011 in San Diego
The 20nm roadmap . TSMC reference flow 12 . The UVM 1.1 release . Verification IP for ARM ACE . Assertion-driven simulation . All of these important items were key EDA360 deliverables this DAC. Yet there was one thing that I dare say was the most anticipated part of the whole conference: of course, I'm...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Mon, Jun 13 2011
Video: New Cadence Verification IP Catalog (With Denali Inside!)
Clearly UVM 1.0 was the main story at DVCon last week, but there was other big news in verification IP that bears repeating. Specifically, last week Cadence announced a new Verification IP ("VIP") Catalog -- a complete combination of standards-based Cadence and ex-Denali verification IP, supporting...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Tue, Mar 8 2011
The Role of Coverage in Formal Verification, Part 1 of 3
As outlined in a prior post , new advances in formal and multi-engine technology (like Incisive Enterprise Verifier or "IEV") enables users to do complete verification of design IP using only assertions (i.e. no testbench required!) -- especially for blocks of around 1 million flops or less...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Mon, Jan 3 2011
Users Employ Specman Constrained-Random Verification for Complex IP
Two recent customer examples have shown the effectiveness of Specman constrained-random verification for complex SoCs. Raimund Soenning, manager of hardware development for the Graphics Competence Center at Fujitsu Semiconductor Europe (Germany), and Sarmad Dahir, ASIC designer at Ericsson (Sweden),...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, Sep 3 2010
Inside Cadence: Training for EDA360
Over the past few weeks all of Cadence's Verification and Systems Solutions Applications Engineers (AEs), Services Engineers, and many Customer Support staff, have been brought together for detailed methodology and product training. The objectives of this ambitious undertaking are to bring their...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Thu, May 6 2010
2010 CDNLive Munich Guide for Specmaniacs
Good news for Specmaniacs based in the EU: next week from May 4-6 is the annual CDNLive! event in Munich. An overview of the conference with info on how to register is here: http://www.cadence.com/cdnlive/eu/2010/pages/agenda.aspx Even better (from a Specmaniac perspective), none other than e /Specman...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, Apr 30 2010
VIP Portfolio Extension: New AMBA 4 Protocol Support
ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing Verification IP (VIP) support for the new AMBA 4 protocol simultaneously with ARM’s introduction of said protocol. Here is the official announcement, which includes AMBA4 and VIP highlights . What this...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Mon, Mar 8 2010
Formalizing Multilanguage Mixology For e Users
Historically it’s been very common for e users to have to mix other programming languages with their e verification environment. Some examples include adding C or C++ reference models, contributing e Universal Verification Components (UVCs) to non- e testbenches, or even interfacing to Matlab models...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Thu, Dec 24 2009
IntelliGen Lab Now Live on Xuropa - See What You Are Missing!
Team Specman guesstimates that a majority of users have migrated to "IntelliGen" -- the all new, Aspect-Oriented generation engine inside of Specman and IES-XL, and/or they are in the process of adopting IntelliGen now. However, in case your CAD configuration is just becoming unfrozen after...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Nov 10 2009
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