Home > Community > Tags > CTS/soc encounter
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

CTS,soc encounter

  • non-clock tree cells on clock tree paths

    Hello, I have a question regarding the use of non-clock tree cells on clock tree paths. The netlist post-synthesis that I have, contains standard muxes and gating-elements on clock paths. During the P&R clock-tree-synthesis step, clock tree buffers are inserted but the standard muxes and gating elements...
    Posted to Digital Implementation (Forum) by chris06 on Fri, Jun 13 2014
  • Re: Clock Tree Synthesis - Not able to add clock buffers

    I have reattached a new cts report. I cannot understand why the actual Max. Rise Sink tran and Max. Fall Sink Tran are so big (would this problem arise from incorrect library characterization?). Please see the attached file for more details. Actual Max. Rise Sink Tran : 391862(ps) Actual Max. Fall Sink...
    Posted to Digital Implementation (Forum) by Northfork on Thu, Apr 25 2013
Page 1 of 1 (2 items)