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CTS

  • *Fence* *SRC* *MME* Buffers in Clock Tree

    With 10.11USR1 enconter we are seeing new type of buffers being added at CTS *MMExc__L1_I0 these kind of naming convention was given if a pin was declared excludedPin in clock spec file but in 10.1 *MMExc* buffers are being added without specfying excludedPin and this is not because of loops in clock...
    Posted to Digital Implementation (Forum) by Nataraja G on Mon, Jun 27 2011
  • Re: How to change use clock on nets?

    Hi Bob, I loaded the clokspec and used the following cmd ckSynthesis -check -forceReconvergent -trace the property on the eco nets in the clk path not updated. but the report file after tracing contains these eco net names. can u please tell how to set clock propery on these nets? Regards suresh
    Posted to Digital Implementation (Forum) by spach on Thu, Oct 7 2010
  • Re: How to change use clock on nets?

    Hi Bob. I inserted clock buffers on some clk nets using ecoAddRepeater, but the new nets after the buffer insertion r not getting the use clk property. can u please tell how i can replicate the clk property for new nets also. Also can u please explain how encounter usually assigns this clock property...
    Posted to Digital Implementation (Forum) by spach on Wed, Oct 6 2010
  • Re: How to change use clock on nets?

    Hi Bob, thank u for u r reply. I am working on a hierarchical design. I need to do buffering on nets across partitions. i have written some db scripts to get startpin and corresponding endpn and used cts spec as shown below(no need of balancing b/w nets). i preffer CTS than BTS as CTS takes less run...
    Posted to Digital Implementation (Forum) by spach on Sun, Oct 3 2010
  • How to change use clock on nets?

    Hi, I used CTS to buffer signal nets in my design at place stage. once the buffering was over I loaded the actual CTS spec and proceed furthur but these nets r having use clock property. Now My design is fully routed, Can any one tell a procedure to change use clock property to signal for these nets...
    Posted to Digital Implementation (Forum) by spach on Sat, Oct 2 2010
  • Re: clock tree synthesis.

    I have many doubts and am encountering many situations in the cadence encounter, first of all i am getting the following error in the clock tree synthesis: **ERROR: (SOCCK-114): No valid clock tree root specified. actually i am using a clock for my module. What may i have done wrong that i got this error...
    Posted to Digital Implementation (Forum) by chaitu1488 on Thu, Jul 29 2010
  • How to find ThroughPin(s) for generated clock

    Hi all, in our design we use a number of generated clocks, i.e. the main clock is for instance divided by 13339. The clock dividers are specified as generated_clock in the SDC file. Now, we would like to build a clock tree for the main clock including the generated clock domains. This should be possible...
    Posted to Digital Implementation (Forum) by MMode on Wed, Jun 30 2010
  • listing all the sinks of a clock

    hi can any one please tell me how can i list all the sink pins for a clock and how to find the farthest sink for that clock? regards suresh
    Posted to Digital Implementation (Forum) by spach on Fri, Oct 23 2009
  • Clock mesh delay calculation

    How are the delays calculated in case of a clock mesh ?
    Posted to Digital Implementation (Forum) by Rajesh Vembu on Tue, Jul 7 2009
  • The Case for Robust Database Access

    The most frequently viewed forum post in the old cdnusers.org "Digital IC->Floorplanning, Place and Route" forum initially started off as a seemingly simple inquiry: "Can CTS Stop Tracing on Hierarchical Module Ports?" From that one question came a number of suggestions and discussion...
    Posted to Digital Implementation (Weblog) by BobD on Sun, Jul 13 2008
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