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CTS clock

  • non-clock tree cells on clock tree paths

    Hello, I have a question regarding the use of non-clock tree cells on clock tree paths. The netlist post-synthesis that I have, contains standard muxes and gating-elements on clock paths. During the P&R clock-tree-synthesis step, clock tree buffers are inserted but the standard muxes and gating elements...
    Posted to Digital Implementation (Forum) by chris06 on Fri, Jun 13 2014
  • CTS for design with multiple power domains

    Hi, I have a power gated domain that I'm trying to implement that I'm having trouble with CTS. I have 2 power domains : base_domain(always on) and gated_domain(power-gated). Both domains have multiple clocks in the domains that I'm trying to synthesize clock tree for. For some reason, when...
    Posted to Digital Implementation (Forum) by fieldy on Thu, Jan 30 2014
  • Using MacroModels for CTS in Encounter

    Hi folks, Someone could tell me setCTSMode options to be used in Encounter 11.1 while implementing CTS using MacroModels ??
    Posted to Digital Implementation (Forum) by AB5001 on Tue, May 28 2013
  • Level of the Clock Tree

    Hi everyone, I wonder if it is possible to specify the level of clock tree to be synthesized in socecounter? I mean tell the tool that I want 3 level tree and that it finds that most suitable? I noticed that there is a option named maxNumLevel in autoCTS specification file. But this command can only...
    Posted to Digital Implementation (Forum) by Yuqi on Mon, Feb 25 2013
  • multi-clock problems

    In my design, there are some generated clocks related to one master clock. How can I align the edges of those clocks? Thank you very much.
    Posted to Digital Implementation (Forum) by quiet on Wed, Feb 13 2013
  • *Fence* *SRC* *MME* Buffers in Clock Tree

    With 10.11USR1 enconter we are seeing new type of buffers being added at CTS *MMExc__L1_I0 these kind of naming convention was given if a pin was declared excludedPin in clock spec file but in 10.1 *MMExc* buffers are being added without specfying excludedPin and this is not because of loops in clock...
    Posted to Digital Implementation (Forum) by Nataraja G on Mon, Jun 27 2011
  • Re: LeafPin usage in CTS

    Does anybody know why network after LeafPin is still checked for clock timing violations (like clock gating hold violation in above example)? Thanks in advance.
    Posted to Digital Implementation (Forum) by MaK78 on Fri, May 13 2011
  • Re: CTS error

    Kari, 1. This is my first run. I generated clock spec using clockDesign command. It doesnot have any "Excluded pins" in it. As i see from the cts log, i think the tool is assigning "Excluded pins" by itself wherever necessary. Am I right? 2. And in the case of converging clock, only...
    Posted to Digital Implementation (Forum) by libinpk on Thu, Jul 8 2010
  • CTS error

    Hi, Im gettin the following during my cts. Can anyone explain what the error and how to get over it? Im using 8.1 Encounter. Any help is greatly appreciated.. Tracing Clock abc/OSOUT ... ** Pin xyz/core/TEST_MUX/p214748365A109/YB is a crossover pin between Clock asdf/CLKOA and abc/OSOUT --- Overlapped...
    Posted to Digital Implementation (Forum) by libinpk on Thu, Jul 8 2010
  • How to find ThroughPin(s) for generated clock

    Hi all, in our design we use a number of generated clocks, i.e. the main clock is for instance divided by 13339. The clock dividers are specified as generated_clock in the SDC file. Now, we would like to build a clock tree for the main clock including the generated clock domains. This should be possible...
    Posted to Digital Implementation (Forum) by MMode on Wed, Jun 30 2010
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