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CPF,low power

A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”

By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer at Maxim Integrated, will be happy to see this...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 13 2013
New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release...

Posted to Low Power (Weblog) by Adam Sherilog on Tue, May 7 2013
Video: What the Newly Approved IEEE 1801-2013 Low Power Format (UPF 2.1) Includes

The IEEE RevCom (Review Committee) approved a new version of the IEEE 1801 low power format, also known as the Unified Power Format (UPF), March 5. The new version is IEEE 1801-2013 or UPF 2.1. It's a significant step towards "methodology convergence" with the Common Power Format (CPF)...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 6 2013
Video, Presentation – Low Power Design with ARM Physical and Processor IP

Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 17 2012
Si2 Talk: Why System-Level Low Power is Challenging

There's a lot of interest in "system level" low power design -- but what does it really mean? "There a lot of confusion," said Pete Hardee, director of solutions marketing at Cadence, in a presentation at the recent Silicon Integration Initiative ( Si2 ) Conference. "What's...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 15 2012
Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year

CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far...

Posted to Low Power (Weblog) by Pete Hardee on Mon, Sep 17 2012
Designer View – Low-Power IC Design Challenges and Solutions

The IC physical design team at Marvell Technology Group Ltd. has a tough challenge. They're under a lot of pressure to minimize power consumption as much as possible, while getting products out the door quickly. In a recorded presentation at the Cadence web site, Murali Natarajan, senior physical...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 23 2012
RAK: Conformal Low Power Advanced Features for Power Intent Comparison, Hierarchical Integration and CPF Macro Modeling

Why do you define macro models? Luke Lang , Engineering Director at Cadence, says that "Just because you have a hard macro doesn't mean you need to define a macro model: A single-domain hard macro without any low power component should be black-boxed. A macro model is not necessary." Luke...

Posted to Low Power (Weblog) by SumeetAggarwal on Fri, Aug 10 2012
Panel: Integrating Low-Power ARM Processors into Mixed-Signal Designs

Mixed-signal chip designs with embedded digital signal processing are becoming more and more commonplace these days. How can you bring low-power processors, such as the ARM Cortex-M0 , into such designs quickly and efficiently? A lunch panel discussion at the recent Design Automation Conference (DAC...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jun 20 2012
What’s Cool for Low-Power at DAC?

Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's...

Posted to Low Power (Weblog) by Pete Hardee on Wed, May 30 2012

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CPF,low power

A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”

New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

Video: What the Newly Approved IEEE 1801-2013 Low Power Format (UPF 2.1) Includes

Video, Presentation – Low Power Design with ARM Physical and Processor IP

Si2 Talk: Why System-Level Low Power is Challenging

Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year

Designer View – Low-Power IC Design Challenges and Solutions

RAK: Conformal Low Power Advanced Features for Power Intent Comparison, Hierarchical Integration and CPF Macro Modeling

Panel: Integrating Low-Power ARM Processors into Mixed-Signal Designs

What’s Cool for Low-Power at DAC?