Cadence.com will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST).
Cadence.com login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Tags > CPF
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

CPF

  • Error Detection for Controlled Voltage Sources and Voltage Scaling

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover error detection. My previous blogs covered some of the following topics: 1. Basics of dynamic power management 2. Very brief introduction to RNM...
    Posted to Low Power (Weblog) by Neyaz on Tue, Sep 21 2010
  • Simulation of Voltage Scaling for Dynamic Power Reduction

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss the simulation of closed-loop voltage scaling for adaptive dynamic voltage and frequency scaling (DVFS). My previous blogs covered some of the...
    Posted to Low Power (Weblog) by Neyaz on Tue, Sep 7 2010
  • Dynamic Power Management – Closed Loop Voltage Scaling

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss open-loop and closed-loop voltage scaling. In previous blogs, I covered some of the following topics: Basics of dynamic power management Very...
    Posted to Low Power (Weblog) by Neyaz on Tue, Aug 24 2010
  • A Call For Power-Aware IP Models

    Power intent formats exist to express the design's low power techniques separately from the design's functional description. This promotes portability of the design across different power schemes. So why are most commercial IP providers forced to bury this critical information deep in gate-level...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Aug 3 2010
  • Q&A: New Challenges, New Solutions In IC Implementation

    Advanced nodes are raising tough new challenges for analog/mixed-signal and digital IC implementation, according to David Desharnais, group director and product manager for implementation at Cadence. In this interview, he notes where IC designers are struggling and succeeding, and describes Cadence's...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 8 2010
  • Low-Power Verification With SystemC - The Great Unknown

    Design teams have used C/C++/SystemC reference models for many years and the trend is growing with SystemC synthesis. At the same time, many teams are adding power-aware structures to their designs and trying to simulate. So what happens when the models encounter unknowns propagated from shutdown blocks...
    Posted to Functional Verification (Weblog) by Team genIES on Thu, Jan 28 2010
  • Adam’s Verification Top 10 In '10

    I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here? Given the breadth of IES (Incisive Enterprise...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 29 2009
  • Are You Playing with a Full Deck?

    A professional gambler confidently place bets because she know the odds, but she would be crazy to play at a table that didn’t use a full deck because the odds change in an unknown way. If you use a simulator that doesn’t enable low-power verification in every test run, you are just as crazy...
    Posted to Functional Verification (Weblog) by Team genIES on Tue, Dec 15 2009
  • Incisive Enterprise Simulator: Low-Power Verification at Warp Speed

    Since your circuit always runs at low-power, your verification should too. To get that "always-on" low-power verification, Incisive Enterprise Simulator (IES) uniquely verifies low-power behaviors natively. In some cases that can result in tests that run faster with power analysis on than with...
    Posted to Functional Verification (Weblog) by Team genIES on Wed, Sep 9 2009
  • User Interview: How Faraday Reduces IC Power Consumption

    Albert Chen, field applications and marketing manager at Faraday Technology , has good news and bad news about low-power IC design. The good news -- low-power design implementation has become much more efficient in the past few years. The bad news -- 60 percent of potential power savings remains untapped...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 19 2009
Page 8 of 10 (94 items) « First ... < Previous 6 7 8 9 10 Next >