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CPF

  • Cadence Low Power Guru Wins Si2’s Distinguished Service Award

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    Posted to Low Power (Weblog) by Pete Hardee on Fri, Oct 21 2011
  • Renamed Si2 Conference Updates EDA Standards

    The Silicon Integration Initiative ( Si2 ) standards organization has held 15 previous OpenAccess Conferences. This year Si2 is calling their annual event, scheduled for Thursday, Oct. 20, the "Si2 Conference." In addition to OpenAccess, the one-day event will provide updates on emerging standards...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 13 2011
  • Managing ECOs in Mixed Signal Designs

    Imagine you are days away from completing the implementation of a fairly complex mixed-signal design, and you are already day-dreaming about the vacation you have planned in a few weeks. Then it happens -- the dreaded change in the design requiring ECOs to digital or analog content, or worse yet, implementation...
    Posted to Mixed-Signal Design (Weblog) by Benatcdn on Thu, Sep 29 2011
  • Another Expert’s View on Power Intent and Hierarchy

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    Posted to Low Power (Weblog) by Pete Hardee on Wed, Sep 21 2011
  • Low-power Keeps Gate-Level Simulation Forever Young

    Ann Mutschler blogged in the Low-Power Engineering Community that gate-level simulation is coming back, driven in part by low-power verification needs. “In a small sense, what’s old is new” may actually be the biggest understatement in her blog. Ann attributes the observation to Cadence’s...
    Posted to Low Power (Weblog) by Adam Sherilog on Thu, Sep 8 2011
  • An Expert’s View on Power Formats and Methodology

    In the last five years since the introduction of power formats, using a side file to describe power intent such as power domains, power modes and associated interface logic has become the mainstream low power design methodology. This marks great progress toward automating complex low power design techniques...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Aug 24 2011
  • Si2’s Steve Schulz: “Setting the Standards for EDA360”

    EDA360 represents a significant change in which the EDA industry plays a broader role in the creation of hardware/software systems ready for applications deployment. A shift this profound must be rooted in industry standards, according to Steve Schulz, president of the Silicon Integration Initiative...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 27 2011
  • User View: Low Power Challenges at 40nm and Below

    Low power design is hard enough at 65nm and above, and it poses additional challenges at 40nm and below, according to Alex Kuo, department manager at SoC design firm Global Unichip Corp. As noted in another Cadence Community blog post by Qi Wang, Kuo offered a presentation on low-power design at the...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 21 2011
  • 8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com

    It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design Automation Conference (DAC) as follows: Are there...
    Posted to Logic Design (Weblog) by David Stratman on Mon, Jun 20 2011
  • Low Power Design -- Alive and Well at DAC

    Low power design was undoubtedly one of the themes of DAC this year -- especially at the Cadence booth. We drew lively interest on the DAC floor with our low power demo station, which was continuously busy especially on the free Monday. We were showing a new demo explaining how advanced low power techniques...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Jun 14 2011
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