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CPF

  • Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!

    CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Mar 7 2012
  • Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

    With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley March 13-14, 2012 will be an exciting forum for Cadence customers to share their most recent chip design successes and learn from each other. Among close to 100 presentations during the packed two day agenda, one area...
    Posted to Mixed-Signal Design (Weblog) by QiWang on Wed, Mar 7 2012
  • Webinar Report: Power-Aware Mixed-Signal Verification

    Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 25 2012
  • What’s Next in Low Power?

    Low power has become a major consideration in chip design in almost all applications. One major achievement of the industry over the past a few years is the alignment on the low power design methodology, which was considered as the biggest hurdle to automate advanced low power design techniques. No matter...
    Posted to Low Power (Weblog) by QiWang on Tue, Jan 24 2012
  • User View: “Multi-Mode” Synthesis Approach Includes Power Optimization

    Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 5 2012
  • Low Power Design in 2011 and Predictions for 2012

    It's that time of year again - winding down towards the end of the year, taking some time with the family, and looking forward to returning refreshed for a new year. So what was the big news for low power in 2011 and what do we have to look forward to in 2012? It's sometimes humbling to look...
    Posted to Low Power (Weblog) by Pete Hardee on Thu, Dec 22 2011
  • 2011 EDA Standards Update and 2012 Forecast

    As system complexity grows and semiconductor process nodes shrink, EDA industry standards are more important than ever. With today's time-to-market pressures, the last thing you'd want to do is waste time due to incompatible formats, tools or methodologies. Fortunately, 2011 was a productive...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 21 2011
  • Si2 Interoperability Guide V2.0 Available for Download

    Recently, the Silicon Integration Initiative (Si2) announced the availability of the Interoperability Guide for Power Format Standards V2.0 . This is an important milestone of power format interoperability between IEEE 1801-2009 and the Common Power Format (CPF). This update was triggered by the Si2's...
    Posted to Low Power (Weblog) by QiWang on Mon, Oct 31 2011
  • ARM TechCon Address: High Stakes at Low Process Nodes

    The complexity of advanced-node IC designs is skyrocketing, and the demands on EDA tool development seem overwhelming - but innovation and deep collaboration will break through the challenges, according to Chi-Ping Hsu, senior vice president for R&D at the Silicon Realization group at Cadence. In...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 25 2011
  • Si2 Conference: New Directions for Low-Power Standards

    The Silicon Integration Initiative (Si2) Conference Oct. 20 provided an ambitious new roadmap for low power standards. Presentations described the current Common Power Format (CPF) 2.0 release, steps towards interoperability with IEEE 1801 (Universal Power Format, UPF), a new approach to power modeling...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 24 2011
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