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CPF,Industry Insights,low power

Video, Presentation – Low Power Design with ARM Physical and Processor IP

Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 17 2012
Si2 Talk: Why System-Level Low Power is Challenging

There's a lot of interest in "system level" low power design -- but what does it really mean? "There a lot of confusion," said Pete Hardee, director of solutions marketing at Cadence, in a presentation at the recent Silicon Integration Initiative ( Si2 ) Conference. "What's...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 15 2012
Designer View – Low-Power IC Design Challenges and Solutions

The IC physical design team at Marvell Technology Group Ltd. has a tough challenge. They're under a lot of pressure to minimize power consumption as much as possible, while getting products out the door quickly. In a recorded presentation at the Cadence web site, Murali Natarajan, senior physical...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 23 2012
Panel: Integrating Low-Power ARM Processors into Mixed-Signal Designs

Mixed-signal chip designs with embedded digital signal processing are becoming more and more commonplace these days. How can you bring low-power processors, such as the ARM Cortex-M0 , into such designs quickly and efficiently? A lunch panel discussion at the recent Design Automation Conference (DAC...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jun 20 2012
System-Level Low Power Design – What Will it Take to Move There?

While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 18 2012
Webinar Report: Power-Aware Mixed-Signal Verification

Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 25 2012
User View: “Multi-Mode” Synthesis Approach Includes Power Optimization

Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 5 2012
ARM TechCon Address: High Stakes at Low Process Nodes

The complexity of advanced-node IC designs is skyrocketing, and the demands on EDA tool development seem overwhelming - but innovation and deep collaboration will break through the challenges, according to Chi-Ping Hsu, senior vice president for R&D at the Silicon Realization group at Cadence. In...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 25 2011
Si2 Conference: New Directions for Low-Power Standards

The Silicon Integration Initiative (Si2) Conference Oct. 20 provided an ambitious new roadmap for low power standards. Presentations described the current Common Power Format (CPF) 2.0 release, steps towards interoperability with IEEE 1801 (Universal Power Format, UPF), a new approach to power modeling...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 24 2011
Renamed Si2 Conference Updates EDA Standards

The Silicon Integration Initiative ( Si2 ) standards organization has held 15 previous OpenAccess Conferences. This year Si2 is calling their annual event, scheduled for Thursday, Oct. 20, the "Si2 Conference." In addition to OpenAccess, the one-day event will provide updates on emerging standards...

Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 13 2011

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CPF,Industry Insights,low power

Video, Presentation – Low Power Design with ARM Physical and Processor IP

Si2 Talk: Why System-Level Low Power is Challenging

Designer View – Low-Power IC Design Challenges and Solutions

Panel: Integrating Low-Power ARM Processors into Mixed-Signal Designs

System-Level Low Power Design – What Will it Take to Move There?

Webinar Report: Power-Aware Mixed-Signal Verification

User View: “Multi-Mode” Synthesis Approach Includes Power Optimization

ARM TechCon Address: High Stakes at Low Process Nodes

Si2 Conference: New Directions for Low-Power Standards

Renamed Si2 Conference Updates EDA Standards