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CONFORMAL

A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”

By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer at Maxim Integrated, will be happy to see this...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 13 2013
New Rapid Adoption Kit (RAK) Enables Productive Mixed-Signal, Low Power Structural Verification

All engineers can enhance their mixed-signal low-power structural verification productivity by learning while doing with a PIEA RAK (Power Intent Export Assistant Rapid Adoption Kit). They can verify the mixed-signal chip by a generating macromodel for their analog block automatically, and run it through...

Posted to Low Power (Weblog) by SumeetAggarwal on Mon, Dec 10 2012
Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via Technologies about strategies they employed to overcome...

Posted to Logic Design (Weblog) by Kenneth Chang on Tue, Nov 27 2012
Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis, Test and Verification Flow were born! What is a RAK...

Posted to Logic Design (Weblog) by SumeetAggarwal on Tue, Jul 24 2012
ENCOUNTER ECO - module

Hi, we use encounter to implement most of our ECO's. However, we have an ECO which requires too many gates. We have heard that some people rip out a module, and have the tool replace the module with the new netlist. The question is what is the procedure to do that? It is easy enough to locate the...

Posted to Digital Implementation (Forum) by checkerbum2 on Tue, Jun 26 2012
Re: LEC - gated clock latches "Unreachable"

Thanks....

Posted to Digital Implementation (Forum) by piyushoct on Mon, May 7 2012
Re: LEC - gated clock latches "Unreachable"

set flatten model -gated_clock will apply on the golden code or revised code? set flatten model -seq_constant will be applied on the golden code or revised code?

Posted to Digital Implementation (Forum) by piyushoct on Sun, May 6 2012
Why Can’t You Write My Assertions for Me? - Part 3

My last two posts have dealt with various forms of automatic assertion creation and assertion synthesis. There is little doubt that these approaches have significant value, complementing and even replacing some of the assertions written by design and verification engineers. However, I started out this...

Posted to Functional Verification (Weblog) by tomacadence on Wed, May 4 2011
Why Can’t You Write My Assertions for Me? - Part 2

In my last post , I described three different types of automatic assertions: those derived from the design, those derived from the design with some assumptions such as naming conventions, and those derived from the design plus supplemental files expressing some aspect of design intent. I finished by...

Posted to Functional Verification (Weblog) by tomacadence on Mon, Apr 25 2011
Why Can’t You Write My Assertions for Me? - Part 1

As regular readers know from previous posts , I have a lot of background in assertion-based verification (ABV) and how assertions are used in simulation and formal analysis. There has been a lot of growth in the use of both assertions and formal since I was first involved in these technologies in 1999...

Posted to Functional Verification (Weblog) by tomacadence on Tue, Apr 5 2011

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CONFORMAL

A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”

New Rapid Adoption Kit (RAK) Enables Productive Mixed-Signal, Low Power Structural Verification

Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose

Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

ENCOUNTER ECO - module

Re: LEC - gated clock latches "Unreachable"

Re: LEC - gated clock latches "Unreachable"

Why Can’t You Write My Assertions for Me? - Part 3

Why Can’t You Write My Assertions for Me? - Part 2

Why Can’t You Write My Assertions for Me? - Part 1