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New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF
On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release...
Posted to
Low Power
(Weblog)
by
Adam Sherilog
on Tue, May 7 2013
Designer View – How GigaOpt in Encounter Digital Implementation (EDI) System 13.1 Boosts IC Design Quality
If you want to design faster chips in a shorter period of time, the new GigaOpt preRoute technology in the EDI System 13.1 release may be the solution. A detailed look at the GigaOpt preRoute technology came from a CDNLive Silicon Valley presentation March 12, 2013, given by Jack Benzel (right), expert...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 1 2013
GLOBALFOUNDRIES at CDNLive: Why 10nm Requires Design Technology Co-Optimization
It's not too early to start thinking about the 10nm process node and beyond - but such advanced process nodes will require a significant change in the semiconductor design ecosystem, according to Jongwook Kye, fellow for lithography modeling and architecture at GLOBALFOUNDRIES. At the recent CDNLive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Apr 29 2013
CDNLive Silicon Valley 2013 Proceedings Available for Download!
CDNLive Silicon Valley, held March 12-13, 2013, featured nearly 100 technical sessions from customers, partners, and Cadence R&D experts. Presentations from most of those sessions are now available on line . Here's your chance to review presentations you heard, catch up on sessions you missed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 4 2013
How Hardware/Software Co-Development Fuels “Product Creation”
I've written recently about "product creation," a concept that looks beyond the chip or board and considers the requirements of the entire end product, including hardware, software applications, and mechanical enclosures. These requirements ripple down through the design supply chain and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 3 2013
Unleashing Mixed-Signal Tech on Tours (ToTs) in North America
At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The key challenges that our mixed-signal customers face...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Fri, Mar 29 2013
Martin Lund CDNLive Keynote: Why SoCs Need “Application Optimized” IP
Systems on chip (SoCs) are incredibly varied, extremely complex, and based on rapidly changing requirements and specifications, according to Martin Lund, senior vice president for R&D at the Cadence SoC Realization Group. At a keynote speech at the CDNLive Silicon Valley conference March 12, 2013...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 14 2013
Samsung CDNLive Keynote: Innovation and Challenges in the Post-PC Era
We are living through a "disruptive" transition in which a PC-driven market is giving way to a mobile-driven market, according to Young Sohn, president and chief strategy officer for device solutions at Samsung Electronics. In a keynote speech March 12, 2013 at the CDNLive Silicon Valley conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 13 2013
Lip-Bu Tan at CDNLive 2013: Opportunities and Challenges for Electronics, and How Cadence Can Help
Lip-Bu Tan, Cadence president and CEO, is excited about ongoing innovation within the electronics industry - but he's also aware of challenges such as advanced node lithography, complexity, time-to-market, and rising design costs. In a keynote speech at the CDNLive Silicon Valley conference March...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 12 2013
CDNLive Paper Preview: RTL Performance Analysis of ARM Interconnect IP
System on chip (SoC) interconnect must meet the performance requirements of increasingly demanding, complex chips -- but traditional modeling and verification techniques don't shed much light on bandwidth and latency. A new approach to analyzing and debugging performance with ARM system IP (interconnect...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 11 2013
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