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CDNlive,Industry Insights
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Designer View – How GigaOpt in Encounter Digital Implementation (EDI) System 13.1 Boosts IC Design Quality
If you want to design faster chips in a shorter period of time, the new GigaOpt preRoute technology in the EDI System 13.1 release may be the solution. A detailed look at the GigaOpt preRoute technology came from a CDNLive Silicon Valley presentation March 12, 2013, given by Jack Benzel (right), expert...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 1 2013
CDNLive Silicon Valley 2013 Proceedings Available for Download!
CDNLive Silicon Valley, held March 12-13, 2013, featured nearly 100 technical sessions from customers, partners, and Cadence R&D experts. Presentations from most of those sessions are now available on line . Here's your chance to review presentations you heard, catch up on sessions you missed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 4 2013
How Hardware/Software Co-Development Fuels “Product Creation”
I've written recently about "product creation," a concept that looks beyond the chip or board and considers the requirements of the entire end product, including hardware, software applications, and mechanical enclosures. These requirements ripple down through the design supply chain and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 3 2013
Martin Lund CDNLive Keynote: Why SoCs Need “Application Optimized” IP
Systems on chip (SoCs) are incredibly varied, extremely complex, and based on rapidly changing requirements and specifications, according to Martin Lund, senior vice president for R&D at the Cadence SoC Realization Group. At a keynote speech at the CDNLive Silicon Valley conference March 12, 2013...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 14 2013
Samsung CDNLive Keynote: Innovation and Challenges in the Post-PC Era
We are living through a "disruptive" transition in which a PC-driven market is giving way to a mobile-driven market, according to Young Sohn, president and chief strategy officer for device solutions at Samsung Electronics. In a keynote speech March 12, 2013 at the CDNLive Silicon Valley conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 13 2013
CDNLive Paper Preview: RTL Performance Analysis of ARM Interconnect IP
System on chip (SoC) interconnect must meet the performance requirements of increasingly demanding, complex chips -- but traditional modeling and verification techniques don't shed much light on bandwidth and latency. A new approach to analyzing and debugging performance with ARM system IP (interconnect...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 11 2013
User View: Going “Green” With Low-Power Design and Clock Concurrent Optimization (CCOpt)
Network processing chips are tough to design. They're big, they're fast, and they have to minimize power consumption. At CDNLive! Silicon Valley 2012 (the Cadence user group conference) Ranjit LoboPrabhu, physical design manager at Netronome Systems , shared some ways his company is going "green"...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 4 2012
CDNLive! Paper –Why Doesn’t My Board Work?
Why would a printed circuit board design go through a CAD system without a hitch, and then produce problems in fabrication or assembly - or worse, fail in the field? A paper at the recent CDNLive! Silicon Valley 2012 (Cadence user group conference) illustrated a number of ways this can happen, and showed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 3 2012
CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning
Double patterning will be an essential lithographic technique for ICs at 20nm and below. The more we can understand it, and quantify its impacts on the design flow, the easier it will be to adopt. A good step towards that understanding was taken at CDNLive! Silicon Valley 2012 (the recent Cadence user...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 1 2012
Don’t Blow Up Your Chip on the Tester!
The photo at right shows a test socket and chip destroyed by thermal runaway. Can this really happen? Yes, it can and it sometimes does, if test power is significantly greater than functional power. To get a handle on this problem I talked to Bassilios Petrakis, product marketing director for Design...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 26 2012
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