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How Debug Breakthroughs are Enabled by In-Circuit Acceleration
We in product management are often accused of jumping the gun and announcing products too fast. Users are looking at press releases and are wondering "sounds great, but does it really work?" Cadence announced earlier this week new in-circuit acceleration capabilities to our System Development...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Wed, May 16 2012
CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Verification
With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High performance...
Posted to
Mixed-Signal Design
(Weblog)
by
AElzeftawi
on Mon, Apr 9 2012
User View: Going “Green” With Low-Power Design and Clock Concurrent Optimization (CCOpt)
Network processing chips are tough to design. They're big, they're fast, and they have to minimize power consumption. At CDNLive! Silicon Valley 2012 (the Cadence user group conference) Ranjit LoboPrabhu, physical design manager at Netronome Systems , shared some ways his company is going "green"...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 4 2012
CDNLive! Paper –Why Doesn’t My Board Work?
Why would a printed circuit board design go through a CAD system without a hitch, and then produce problems in fabrication or assembly - or worse, fail in the field? A paper at the recent CDNLive! Silicon Valley 2012 (Cadence user group conference) illustrated a number of ways this can happen, and showed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 3 2012
CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning
Double patterning will be an essential lithographic technique for ICs at 20nm and below. The more we can understand it, and quantify its impacts on the design flow, the easier it will be to adopt. A good step towards that understanding was taken at CDNLive! Silicon Valley 2012 (the recent Cadence user...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 1 2012
CDNLive! -- The Other Side of the Low Power Design Techniques
In a recent CDNLive! Silicon Valley presentation titled "Low Power Implementation on the Freescale Kinetis Family," Annis Jarrar from Freescale demonstrated how various low power design techniques were used in the popular Kinetis low power platform. These techniques included power gating with...
Posted to
Low Power
(Weblog)
by
QiWang
on Thu, Mar 29 2012
Don’t Blow Up Your Chip on the Tester!
The photo at right shows a test socket and chip destroyed by thermal runaway. Can this really happen? Yes, it can and it sometimes does, if test power is significantly greater than functional power. To get a handle on this problem I talked to Bassilios Petrakis, product marketing director for Design...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 26 2012
CDNLive Silicon Valley 2012: Much More than Moore
Last week I had the pleasure of meeting dozens of customers at CDNLive! Silicon Valley, and learning from the keynotes, in-depth technical papers, and synchronistic conversations throughout the event. Below are some highlights and themes that emerged. Left to right: Keynote speakers Lip-Bu Tan (Cadence...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Tue, Mar 20 2012
CDNLive! Keynote – New Horizons for ARM Based SoCs
30 billion ARM-based chips have shipped over the last 20 years, but ARM isn't stopping there. ARM is looking beyond cell phones and mobile devices and pursuing new opportunities in the server, home entertainment, and automotive marketplaces, according to Tom Lantzsch (right), executive vice president...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 15 2012
CDNLive! – Lip-Bu Tan Keynote Cites Semiconductor Growth Drivers
CDNLive! Silicon Valley , the annual Cadence U.S. user conference, opened in San Jose, California March 13, 2012 on an optimistic yet cautionary note. Keynote speakers from Cadence, TSMC and ARM each predicted a new era of innovation in the electronics industry, but also noted daunting challenges that...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 13 2012
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