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CDN Live

User View: Broadcom Evaluates Clock Concurrent Optimization (CCOpt)

Clock concurrent optimization (CCOpt) is a new technology that runs clock tree synthesis (CTS) concurrently with physical optimization. It claims significant improvements in performance, power, and area - but the only way to really quantify such claims is through customer experience with real designs...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 23 2012
CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Verification

With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High performance...

Posted to Mixed-Signal Design (Weblog) by AElzeftawi on Mon, Apr 9 2012
User View: Going “Green” With Low-Power Design and Clock Concurrent Optimization (CCOpt)

Network processing chips are tough to design. They're big, they're fast, and they have to minimize power consumption. At CDNLive! Silicon Valley 2012 (the Cadence user group conference) Ranjit LoboPrabhu, physical design manager at Netronome Systems , shared some ways his company is going "green"...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 4 2012
CDNLive! Paper –Why Doesn’t My Board Work?

Why would a printed circuit board design go through a CAD system without a hitch, and then produce problems in fabrication or assembly - or worse, fail in the field? A paper at the recent CDNLive! Silicon Valley 2012 (Cadence user group conference) illustrated a number of ways this can happen, and showed...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 3 2012
CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning

Double patterning will be an essential lithographic technique for ICs at 20nm and below. The more we can understand it, and quantify its impacts on the design flow, the easier it will be to adopt. A good step towards that understanding was taken at CDNLive! Silicon Valley 2012 (the recent Cadence user...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 1 2012
CDNLive! -- The Other Side of the Low Power Design Techniques

In a recent CDNLive! Silicon Valley presentation titled "Low Power Implementation on the Freescale Kinetis Family," Annis Jarrar from Freescale demonstrated how various low power design techniques were used in the popular Kinetis low power platform. These techniques included power gating with...

Posted to Low Power (Weblog) by QiWang on Thu, Mar 29 2012
CDNLive! Keynote – New Horizons for ARM Based SoCs

30 billion ARM-based chips have shipped over the last 20 years, but ARM isn't stopping there. ARM is looking beyond cell phones and mobile devices and pursuing new opportunities in the server, home entertainment, and automotive marketplaces, according to Tom Lantzsch (right), executive vice president...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 15 2012
TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”

The world's largest foundry provider, TSMC, is confident it can keep up with the semiconductor scaling predicted by Moore's Law and can even outpace Moore's Law through 2.5D and 3D-ICs. It's all part of the "incredible high-tech future" predicted by Rick Cassidy, president of...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 14 2012
CDNLive! – Lip-Bu Tan Keynote Cites Semiconductor Growth Drivers

CDNLive! Silicon Valley , the annual Cadence U.S. user conference, opened in San Jose, California March 13, 2012 on an optimistic yet cautionary note. Keynote speakers from Cadence, TSMC and ARM each predicted a new era of innovation in the electronics industry, but also noted daunting challenges that...

Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 13 2012
CDNLive! Silicon Valley – Agenda Set, Registration Open, $99 Deal

CDNLive! Silicon Valley, the Cadence user conference for the U.S., is set for San Jose, California March 13-14 at the DoubleTree Hotel. An agenda and registration information are now available on line , and there's a special "early bird" $99 registration deal if you sign up before January...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 12 2012

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CDN Live

User View: Broadcom Evaluates Clock Concurrent Optimization (CCOpt)

CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Verification

User View: Going “Green” With Low-Power Design and Clock Concurrent Optimization (CCOpt)

CDNLive! Paper –Why Doesn’t My Board Work?

CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning

CDNLive! -- The Other Side of the Low Power Design Techniques

CDNLive! Keynote – New Horizons for ARM Based SoCs

TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”

CDNLive! – Lip-Bu Tan Keynote Cites Semiconductor Growth Drivers

CDNLive! Silicon Valley – Agenda Set, Registration Open, $99 Deal