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CDL

  • netlist pin order for LVS

    Hi, I'm trying to change the order in which a circuit is netlisted for LVS but I got into problems. I've modified the termOrder in the CDF form accoding to the pin order I want and I've place the following line in ~/.simrc (and also in my cadence working dir): auCdlCDFPinCntrl=t I've...
    Posted to Custom IC SKILL (Forum) by NcfC on Thu, Mar 6 2014
  • Modify netlist of a block and resimulate (CDL.... CDF....)

    Hello everyone, I am trying to pinpoint a layout error mechanism by modifying the av_extracred view netlist and resimulating the testbench. I have managed to create a manually written netlist as a spectre view before by following this tutorial: http://www.cadence.com/Community/blogs/rf/archive/2009/01...
    Posted to Custom IC Design (Forum) by cozdag on Sat, Dec 28 2013
  • Support for Low Power Mixed Signal Designs in Virtuoso Schematic-XL

    Why is There a Need for Low Power Solutions? With an increase in the demand for high-performance, multi-tasking systems-on-chips (SoCs) for communication and computing, the power requirements for these electronic chips have also greatly increased. There has been a surge in the production of portable...
    Posted to Mixed-Signal Design (Weblog) by DeveshJain on Tue, Dec 10 2013
  • Reverse Netlist creation question

    So I am attempting to do something here that I have never done in Cadence. I have tried various approaches throughout the day and have gotten no where. Env: cadence IC514 (not my choice), using PVS DRC/LVS Objective: I was asked to resurrect an old design and import it into a new project env. The design...
    Posted to Custom IC Design (Forum) by srftech on Wed, Sep 5 2012
  • Re: stream Out using SKILL

    I finally managed to stream out my cdl netlis. I used the following code (in case anyone wants to use it) strmOutCDLName = buildString( list( cell "src" "net" ) "." ) cdlOutKeys = list(nil 'cdsNetlistingMode "Analog" 'runInBackground 'nil 'simStopList...
    Posted to Custom IC SKILL (Forum) by ahata on Tue, Jul 26 2011
  • Re: stream Out using SKILL

    Hi, I would like to know how to get CDL files using SKILL code similar to what is done with the gds if there is a way. So is there any function for cdl export that would do the same as the xstOutDoTranslateto stream out gds files??? I try using the cdlOutKeys parameter to configure the cdl extractio0n...
    Posted to Custom IC SKILL (Forum) by ahata on Thu, Jul 21 2011
  • Re: stream Out using SKILL

    Hi, I would like to know how to get CDL files using SKILL code similar to what is done with the gds if there is a way. So is there any function for cdl export that would do the same as the xstOutDoTranslateto stream out gds files??? I try using the cdlOutKeys parameter to configure the cdl extractio0n...
    Posted to Custom IC SKILL (Forum) by ahata on Thu, Jul 21 2011
  • Using Spice Models/Netlists with icfb

    Hi all, I'm pretty new to the Cadence Environment and now I've got the task to make some simulations including some commercial PSpice models within the Cadence Environment (icfb, Virtuoso etc.). I found some information on the internet saying that this task could be done using "CDL in.....
    Posted to Custom IC Design (Forum) by mixedsignal on Tue, Dec 7 2010
  • cdl export error when lvs with dracula

    Hi everybody... cdl export error when lvs with dracula.error:unable to descend into any of the views defined in the view list :“aucdl schematic” for instance I120 in the cell mult4.But I do not find the I120 in the schematic .After I corrected some instances the error appeared. Thanks
    Posted to Custom IC Design (Forum) by kobe0704 on Tue, Dec 7 2010
  • Unable to export CDL file

    Hi, I tried to export a cdl file from a small cell sw_dummy(it contains only basic MOS transistors), although it succeeded, the netlist was empty. Then I tried to export the cdl from Calibre LVS function, but it failed. The error I get is: Netlister: unable to descend into any of the views defined in...
    Posted to Custom IC Design (Forum) by Renee on Mon, Aug 9 2010
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