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C-to-silicon

C-to-Silicon Compiler 10.1 - Ease Of Use And RTL QoR

In the continuing effort to make high-level synthesis more viable to mainstream RTL designers, Cadence has released version 10.1 of the Cadence C-to-Silicon Compiler (CtoS). This new release continues the recent trend towards overall ease-of-use and Quality of Results. The already popular CtoS GUI has...

Posted to System Design and Verification (Weblog) by Steve Brown on Wed, Jun 2 2010
When Will We Move From RTL to TLM? I Need to Know!

My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point so that we can learn from history. He lists a...

Posted to Logic Design (Weblog) by Jack Erickson on Mon, Mar 8 2010
DVCon SystemC Day Quandry: Need for Third Party TLM IP

Sometimes in the most optimistic of discussions, there is an "elephant in the room" that people don't say much about. Such was the case at the DVCon SystemC Day Feb. 22, where despite strong attendance and upbeat presentations, there was only a small amount of discussion about the need...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 24 2010
Q&A: How System Design And Verification Can Go “Mainstream”

System design and verification are part of the RTL flow today, but a higher level of abstraction is now poised to enter the IC design mainstream, according to Ran Avinun, marketing group director for system design and verification at Cadence. In this interview he discusses trends in hardware/software...

Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 18 2010
Methodology Is Important But Language Matters - Part 1

Historical trends in languages Many of us have traveled around the world, and while we can often communicate with local people in our own language, we realize it is best to communicate using the local language. It helps to "break the ice" if you at least try to use some of the local language...

Posted to System Design and Verification (Weblog) by Ran Avinun on Tue, Jan 26 2010
RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!

I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize in conjunction with placement. It also goes on...

Posted to Logic Design (Weblog) by Jack Erickson on Mon, Jan 25 2010
Q&A: Michał Siwiński Sees Major Shift in Product Design and Verification

The rising costs of product development are causing fundamental changes in the design and verification flows, according to Michał Siwiński, group director of front-end product management at Cadence. In this interview he discusses customer challenges and Cadence strategies in such areas as hardware/software...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 6 2010
Wrapping Up 2009 With Some Reflections

As many of my customers mentioned and no surprise, 2009 was a tough year. Regardless though, designs continued to get pumped out the door by aggressive design teams, putting products in eager customer hands. I constantly get mesmerized by the number of people who are buying iPhones, including co-workers...

Posted to Logic Design (Weblog) by Kenneth Chang on Wed, Dec 23 2009
Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself!

Last week Cadence’s new CMO John Bruggeman extended a personal invitation to all of you to join us for CDNLive San Jose 2009 . With 60+ papers, tutorials, and workshops, live and webcasted, we’re expecting even bigger attendance than back in 2007 (our biggest ever). Those of you attending...

Posted to System Design and Verification (Weblog) by SteveSvoboda on Sat, Oct 3 2009
Q&A Interview: Nimish Modi Describes Front End ‘Paradigm Shift’

Nimish Modi is senior vice president for front end research and development at Cadence. In this interview, he discusses Cadence’s front end strategy in such areas as low power, mixed signal, system development, enterprise verification and predictive design. He also explains why he thinks EDA technology...

Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 10 2009

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C-to-silicon

C-to-Silicon Compiler 10.1 - Ease Of Use And RTL QoR

When Will We Move From RTL to TLM? I Need to Know!

DVCon SystemC Day Quandry: Need for Third Party TLM IP

Q&A: How System Design And Verification Can Go “Mainstream”

Methodology Is Important But Language Matters - Part 1

RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!

Q&A: Michał Siwiński Sees Major Shift in Product Design and Verification

Wrapping Up 2009 With Some Reflections

Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself!

Q&A Interview: Nimish Modi Describes Front End ‘Paradigm Shift’