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C-to-Silicon

What Does SystemC Mean for Design and Verification?

My colleague Jack Erickson recently published in the Cadence System Design and Verification Community a blog post entitled "IP Cannot Be an Efficient Abstraction Level without SystemC!" When I saw the title, my immediate reaction was to write a complementary post called "SystemC Cannot...

Posted to Functional Verification (Weblog) by tomacadence on Tue, Aug 23 2011
Calypto CEO Interview: Why System Realization Needs Sequential Analysis

One important enabling technology of a transaction-level modeling (TLM) based design flow is an ability to verify the results of high-level synthesis. Calypto Design Systems , a member of the recently-formed Cadence System Realization Alliance , is playing an important role by closely integrating its...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 2 2010
New Era Of SoC Design – Still Enabled By Logic Designers

If you were unable to attend Embedded/SoC Enablement Day at DAC, I encourage you to check out Richard Goering's writeup on the new era of SoC design being driven by applications . It describes how Gadi Singer of Intel discussed new TVs that are networked and can run apps on them (which for me is...

Posted to Logic Design (Weblog) by Jack Erickson on Thu, Jul 8 2010
TSMC Reference Flow Adds TLM Support -- Here's Why

Every year as spring turns to summer, we can count on a new Reference Flow from TSMC. While the seasons are driven by the laws of nature, the Reference Flow is driven by the laws of Moore. Typically the new additions to the flow have to do with accounting for new process effects such as signal integrity...

Posted to Logic Design (Weblog) by Jack Erickson on Fri, Jun 11 2010
C-to-Silicon Compiler 10.1 - Ease Of Use And RTL QoR

In the continuing effort to make high-level synthesis more viable to mainstream RTL designers, Cadence has released version 10.1 of the Cadence C-to-Silicon Compiler (CtoS). This new release continues the recent trend towards overall ease-of-use and Quality of Results. The already popular CtoS GUI has...

Posted to System Design and Verification (Weblog) by Steve Brown on Wed, Jun 2 2010
When Will We Move From RTL to TLM? I Need to Know!

My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point so that we can learn from history. He lists a...

Posted to Logic Design (Weblog) by Jack Erickson on Mon, Mar 8 2010
DVCon SystemC Day Quandry: Need for Third Party TLM IP

Sometimes in the most optimistic of discussions, there is an "elephant in the room" that people don't say much about. Such was the case at the DVCon SystemC Day Feb. 22, where despite strong attendance and upbeat presentations, there was only a small amount of discussion about the need...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 24 2010
Q&A: How System Design And Verification Can Go “Mainstream”

System design and verification are part of the RTL flow today, but a higher level of abstraction is now poised to enter the IC design mainstream, according to Ran Avinun, marketing group director for system design and verification at Cadence. In this interview he discusses trends in hardware/software...

Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 18 2010
Methodology Is Important But Language Matters - Part 1

Historical trends in languages Many of us have traveled around the world, and while we can often communicate with local people in our own language, we realize it is best to communicate using the local language. It helps to "break the ice" if you at least try to use some of the local language...

Posted to System Design and Verification (Weblog) by Ran Avinun on Tue, Jan 26 2010
RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!

I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize in conjunction with placement. It also goes on...

Posted to Logic Design (Weblog) by Jack Erickson on Mon, Jan 25 2010

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C-to-Silicon

What Does SystemC Mean for Design and Verification?

Calypto CEO Interview: Why System Realization Needs Sequential Analysis

New Era Of SoC Design – Still Enabled By Logic Designers

TSMC Reference Flow Adds TLM Support -- Here's Why

C-to-Silicon Compiler 10.1 - Ease Of Use And RTL QoR

When Will We Move From RTL to TLM? I Need to Know!

DVCon SystemC Day Quandry: Need for Third Party TLM IP

Q&A: How System Design And Verification Can Go “Mainstream”

Methodology Is Important But Language Matters - Part 1

RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!