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C-to-Silicon Compiler
Acceleration
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System Design and Verification
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How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?
During the planning phase for SoC designs, teams have to choose whether to "make or buy" the pieces of IP that will compose the SoC. The drivers of this decision are well-chronicled in a recent article by Ann Steffora Mutchler, appropriately titled "Make vs. Buy". I won't re-hash...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Nov 22 2011
17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction Design and Verification?
In their presentation at the recent SystemC Japan conference, Renesas Micro Systems, Inc. (RMS) stated 2 SystemC "beginners" completed a 17M gate design in 8 months, achieving first-pass timing closure at 650 MHz targeting 40nm. Two thoughts came to my mind: Wow! What is their ROI of migrating...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Oct 4 2011
Q&A: Linking Virtual Prototypes to High-Level Synthesis
Virtual prototypes for early software development and high-level synthesis tools for hardware implementation are two important new technologies that are raising the abstraction level in electronic systems design. But these tools are traditionally isolated from one another because they require different...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 29 2011
System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part II)
2010 was a very dynamic year for the electronic systems industry overall and Cadence in particular. In this set of blogs, I discuss some of the trends that started in 2010 and will continue in 2011. In part I, I talked about the key growth market, key industry challenges and the role of EDA. In this...
Posted to
System Design and Verification
(Weblog)
by
Ran Avinun
on Tue, Dec 28 2010
System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part 1)
2010 was a very dynamic year for the electronic systems industry overall, and for Cadence in particular. In the next couple of blogs, I would like to focus on some of the trends that started in 2010 and will continue in 2011. In this blog (part I), I will talk about the key growth markets, key industry...
Posted to
System Design and Verification
(Weblog)
by
Ran Avinun
on Thu, Dec 16 2010
Q&A: What Cadence Has Learned About High Level Synthesis
With the recent release of Cadence C-to-Silicon Compiler, Cadence has joined the rapidly growing high-level synthesis (HLS) marketplace. In this interview Mike "Mac" McNamara, vice president and general manager of the Cadence Systems Software Group, talks about what Cadence has discovered about...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 24 2010
Methodology Is Important But Language Matters - Part 2
In this blog, I would like to discuss the direction in the languages that will be chosen for TLM (or ESL) verification. Transaction-Level Models have been used for long time as simulation models. As we start to use more and more high-level synthesis, the link to design and implementation is becoming...
Posted to
System Design and Verification
(Weblog)
by
Ran Avinun
on Tue, Feb 9 2010
Imitation Is The Sincerest Form Of Flattery - We Thank You!
Let me start by sharing some recent blog activity showing competitors doing some admittedly admirable marketing work . Check it out. They write well, gather some good data, etc. All "good stuff" to help customers like you make an "informed decision". In the spirit of sharing other...
Posted to
System Design and Verification
(Weblog)
by
Steve Brown
on Mon, Dec 21 2009
Q&A Interview: Chris Tice Outlines Cadence System Level Design Strategy
Chris Tice is the senior vice president and general manager for System Design and Verification at Cadence Design Systems. In this interview, he discusses upcoming and ongoing developments with transaction-level IP design, virtual platforms, embedded software verification, and system-level low power design...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 8 2009
Synthesis Really DOES Need to Change
A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, “ Synthesis Needs to Change to Serve Modern Chip Design ”. Tets Maniwa is sharp guy. (Those of you designing ICs in the mid/late 1990s probably remember a wonderful magazine called “Integrated System Design”...
Posted to
System Design and Verification
(Weblog)
by
SteveSvoboda
on Tue, Jun 2 2009
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