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Assura,error markers

  • Assura error markers not viewable when zoomed out

    Hi, Previously, our layout designers were accustomed to doing a "fit zoom" and viewing the entire chip. At this perspective, with all layout layers set to no-view, they could see all the Assura DRC error markers. (It's an informal tape-out, sign-off test.) However, for some reason, they...
    Posted to Custom IC Design (Forum) by TrevorB on Tue, Dec 15 2009
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