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Assura

  • Custom Inductor | INDDEF layer | HitKit | Assura

    Hi, this post isin reference to http://www.cadence.com/community/forums/T/14022.aspx , where i described problems concerning an inductor that had been automatically generated by VPCD tool. Defining the layout of the inductor as a blackBox does not solve the problem, for assura does not recognize pins...
    Posted to Custom IC Design (Forum) by pitter on Tue, Dec 1 2009
  • How to modify a automatically generated instance.

    Hi, After inductor cell generation (done with Passive Component Designer - PSD) I made DRC check, that found errors in the layout schematic. The problem is that some vias are placed too near to the edge of the polysilicon Patterned Ground Shield - PGD. I tried to remove the vias or correct the layout...
    Posted to RF Design (Forum) by pitter on Thu, Nov 5 2009
  • ASSURA RCX | capgen error

    Hi, After successful DRC and LVS verification RCX (C extraxtion) fails with the following error: *ERROR* at "capgen": -res_blocking mask layer 'rblock_poly1' not defined in LVS file quitting. I have set the correct technology, the variable netlisting_mode is set to Analog. I also tried...
    Posted to Custom IC Design (Forum) by pitter on Tue, Nov 3 2009
  • Does Assura version affect QRC

    Hi, I'm trying to setup QRC and I've followed the manual by adding the following: In the csh file: setpath = ($EXT_8_1_4/tools/bin $path) In the cds file: setenv QRC_HOME usr/cds/ext-8.1.4 However QRC is not showing up in the menu on the virtuoso layout editor. I'm using IC 5.1.41 latest...
    Posted to Custom IC Design (Forum) by Jsierra on Wed, Oct 7 2009
  • Assura Foundry Support

    I've been blogging a lot about Assura recently, so I thought I would continue by talking about rule decks. Inside Cadence, we maintain a database that shows which foundries support which process for which products. This means that we can quickly give you an answer if you are considering using a new...
    Posted to Silicon Signoff and Verification (Weblog) by ChrisClee on Mon, Mar 23 2009
  • Assura On Steroids

    In a recent post , I hinted at a significant performance improvement in Assura . Our R&D team focused on performance improvements in the 3.2 release, which was shipped last August. Based on our suite of performance benchmarks, we achieved an overall 10x performance boost. This comes from two fundamental...
    Posted to Silicon Signoff and Verification (Weblog) by ChrisClee on Tue, Mar 17 2009
  • ERC in Assura II

    In my last post I talked about the layout, schematic and netlist ERC capabilities of Assura. "But", I hear you ask, "is it programmable?" One of the characteristics that makes Assura such a natural fit within the Virtuoso custom design platform is that it shares the platform's...
    Posted to Silicon Signoff and Verification (Weblog) by ChrisClee on Tue, Mar 10 2009
  • ERC in Assura

    A few customers have recently asked whether we can provide schematic-based ERC checks. This is no doubt spurred by a recent product announcement by one of our competitors. No - I'm not going to say who, and I'm not going to provide a link to their product page. We have had layout-based ERC checks...
    Posted to Silicon Signoff and Verification (Weblog) by ChrisClee on Thu, Mar 5 2009
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