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Assura

  • Why Assura extract 2 more pins for each standard cell?

    Hi Guys, I got a problem when I did blackbox LVS. The reported issue is "pin mismatch" for each standard cell. For example, cell CLKINVX12 has 4 pins in schematic (A Y VDD VSS), but in layout netlist Assura extracts 6 pins (A Y VDD VSS avC5 avS10). In the standard cell layout, I only can see...
    Posted to Digital Implementation (Forum) by laowang on Tue, Mar 27 2012
  • ASSURA DRC error file instance name & error location

    Hi , I have some problem with ASSURA DRC error file . The DRC run generates .err file which can be read by any standard text editor. The problem I am facing is from the text file, some instance names specially mosiacs are named in some strange manner . Also some of the locations of the the error is also...
    Posted to Custom IC SKILL (Forum) by Aritra on Tue, Oct 18 2011
  • How to perform Post-Layout simulations using UltraSim for Black-Box Cells?

    I hope you all are doing fine. I need some guidance regarding post-layout simulation of black-box digital cells from Artisan Standard Cell Library using Ultrasim. We have the verilog, lef and tlf files in the PDK along with CDB symbol database that we converted to OA database. We have imported verilog...
    Posted to Custom IC Design (Forum) by BraveHeart on Wed, Oct 12 2011
  • Any way to Abort Assura LVS run after input layers read ?

    We have a process with multiple variations that include slightly different input layers. To handle the variations within the same LVS file, we have switches. However, if a user is running process variation A and accidentally chooses the swtich to run variation B (having different input layers) , is there...
    Posted to Custom IC Design (Forum) by jm3395 on Wed, Mar 23 2011
  • Assura 4.1 Error Report and Probing

    Hi all, Up to now I have used Assura 3.0/3.1 for LVS and I was used to use the "Error Report" for probing problematic nets and devices. In fact this worked much better for me than the LVS Debug Enviroment. Now I have my first contact with Assura 4.1 and as it seems there is not probing capability...
    Posted to Custom IC Design (Forum) by baenisch on Mon, Nov 8 2010
  • Assura Directory Creation

    Hello, I'm new to Assura (in the past I used Hercules) and I have found the form quite annoying, so what I would like to is automatically load the Run Directory, while also create the Run Directory from cadence using the Library name and Cell Name. So what I was think is creating a bindKey that would...
    Posted to Custom IC SKILL (Forum) by Patrick1982 on Thu, Oct 28 2010
  • Open Instance connections Assura LVS error

    Simple inverter as a Ring Oscillator Design is DRC clean but the Assura LVS brings up Nets Mismatch Tool...Open Instance Connections... I've tried severval ways to remove error but to no avail. Any insight will be appreciated. attach are the screen shot
    Posted to Custom IC Design (Forum) by jdgriggs on Mon, Oct 11 2010
  • Assura DRC/LVS/RCX batch run with SKILL

    Hello, Can somebody please explain how to start Assura DRC/LVS/RCX with a SKILL script? I need to run these checks on an entire library with cells and I have no idea about hot to make a batch run. 10x a lot!
    Posted to Custom IC SKILL (Forum) by Karagyaurov on Wed, Sep 8 2010
  • Assura error markers not viewable when zoomed out

    Hi, Previously, our layout designers were accustomed to doing a "fit zoom" and viewing the entire chip. At this perspective, with all layout layers set to no-view, they could see all the Assura DRC error markers. (It's an informal tape-out, sign-off test.) However, for some reason, they...
    Posted to Custom IC Design (Forum) by TrevorB on Tue, Dec 15 2009
  • Assura RCX fails

    Hi! When running RCX extraction with RC option (there is no error when Only C extraction is performed)I get the following error: /home/piter/Cadence/Assura/tools.lnx86/assura/bin/32bit/labprint: relocation error: /home/piter/Cadence/Assura/tools.lnx86/assura/bin/32bit/labprint: symbol errno, version...
    Posted to Custom IC Design (Forum) by pitter on Fri, Dec 4 2009
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