Home > Community > Tags > Assura
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Assura

  • ASSURA LVS RUN failure: asks OA22.41.010 API

    Hi everyone, I have been struggling with ASSURA LVS, The DRC runs fine however when LVS is run, the following error appears in the error log: Error: failed to initialize OpenAccess because: Requested minor API version '202' which is supported by OpenAccess build '22.41.010' is newer than...
    Posted to Custom IC Design (Forum) by Usama Awais on Sat, Feb 8 2014
  • LVS assura error "Unbound Pin"

    Hi, I'm currently completing my first layout, and getting errors on all my pins. When I run LVS I am getting an error on each saying "Unbound Pin". I have simply placed the pins that were automatically generated in layout XL (when I generated the layout from schematic) within the appropriate...
    Posted to Custom IC Design (Forum) by KipD on Tue, Feb 4 2014
  • Extraction AS/AD in Assura RCX

    Hello. I have a trouble with RCX extraction. After running RCX (output format is Extracted View ) AS/AD, PS/PD parameters in my MOSFETs is zero. However when output format is LVS Extracted View all parameters are correct. Parameter ExtractMOSDiffusionAP=t when running RCX. What I must to do, that AS...
    Posted to Custom IC Design (Forum) by TiNat on Mon, Oct 21 2013
  • Assura, LVS net mismatch but net doesn't exist

    Hi. The messages given to me by Assura use names of devices and nets that I didn't assign. I assume that they are assigned by Assura and that there's a way to search for these nets but I haven't found it. Example names include nets: avC3, avC5. Example devices: avD20_1. Zooming in and/or...
    Posted to Functional Verification (Forum) by TSmilkstein on Tue, Oct 15 2013
  • An urgent problem with the design rule check using Assura

    When I use Assura to do the design rule check after I have done layout using the C35B4 technology in Cadence, there is always a following probleme: [1] #INFO: C35B4/C35B3 ASSURA DRC DECK(REV9 DATE 26-Apr-2011) Last modified 15-Jun-2012. does anyone know why? Thank you advance for you response.
    Posted to Custom IC Design (Forum) by UUinfini on Fri, Jun 14 2013
  • compatibility of Assura 3.1 for 65 nm process

    Hi, I have been using Assura 3.1 for DRC,LVS and extraction for 0.35 um cmos process and now we have been using 65 nm process. Does this Assura is capable for DRC, LVS and including extraction for 65 nm cmos process.
    Posted to Custom IC Design (Forum) by Jithin on Sat, May 25 2013
  • Assura: Include other files

    Hi everyone! Is it possible to split up an Assura rule file into several subfiles and include them into the main rule file which is loaded by the RSF-file? Calibre provides this feature and I really appreciate it for a clear structure. Thanks in advance! Regards!
    Posted to Custom IC Design (Forum) by PekkaH on Thu, Oct 4 2012
  • Running Cadence IC on VMware?

    My IT department is very enthusastic about putting everything on VMware. They say that this will make their job much easier. I would like to know if you, anyone, or your company has tried running Cadence IC, ADE, or Virtuososo (any version) on VMware and how it worked out for you.
    Posted to Custom IC Design (Forum) by John Reeder on Fri, Apr 6 2012
  • Why Assura extract 2 more pins for each standard cell?

    Hi Guys, I got a problem when I did blackbox LVS. The reported issue is "pin mismatch" for each standard cell. For example, cell CLKINVX12 has 4 pins in schematic (A Y VDD VSS), but in layout netlist Assura extracts 6 pins (A Y VDD VSS avC5 avS10). In the standard cell layout, I only can see...
    Posted to Digital Implementation (Forum) by laowang on Tue, Mar 27 2012
  • ASSURA DRC error file instance name & error location

    Hi , I have some problem with ASSURA DRC error file . The DRC run generates .err file which can be read by any standard text editor. The problem I am facing is from the text file, some instance names specially mosiacs are named in some strange manner . Also some of the locations of the the error is also...
    Posted to Custom IC SKILL (Forum) by Aritra on Tue, Oct 18 2011
Page 1 of 3 (26 items) 1 2 3 Next >