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Assura

  • An urgent problem with the design rule check using Assura
    When I use Assura to do the design rule check after I have done layout using the C35B4 technology in Cadence, there is always a following probleme: [1] #INFO: C35B4/C35B3 ASSURA DRC DECK(REV9 DATE 26-Apr-2011) Last modified 15-Jun-2012. does anyone know why? Thank you advance for you response.
    Posted to Custom IC Design (Forum) by UUinfini on Fri, Jun 14 2013

  • compatibility of Assura 3.1 for 65 nm process
    Hi, I have been using Assura 3.1 for DRC,LVS and extraction for 0.35 um cmos process and now we have been using 65 nm process. Does this Assura is capable for DRC, LVS and including extraction for 65 nm cmos process.
    Posted to Custom IC Design (Forum) by Jithin on Sat, May 25 2013

  • Assura: Include other files
    Hi everyone! Is it possible to split up an Assura rule file into several subfiles and include them into the main rule file which is loaded by the RSF-file? Calibre provides this feature and I really appreciate it for a clear structure. Thanks in advance! Regards!
    Posted to Custom IC Design (Forum) by PekkaH on Thu, Oct 4 2012

  • Running Cadence IC on VMware?
    My IT department is very enthusastic about putting everything on VMware. They say that this will make their job much easier. I would like to know if you, anyone, or your company has tried running Cadence IC, ADE, or Virtuososo (any version) on VMware and how it worked out for you.
    Posted to Custom IC Design (Forum) by John Reeder on Fri, Apr 6 2012

  • Why Assura extract 2 more pins for each standard cell?
    Hi Guys, I got a problem when I did blackbox LVS. The reported issue is "pin mismatch" for each standard cell. For example, cell CLKINVX12 has 4 pins in schematic (A Y VDD VSS), but in layout netlist Assura extracts 6 pins (A Y VDD VSS avC5 avS10). In the standard cell layout, I only can see...
    Posted to Digital Implementation (Forum) by laowang on Tue, Mar 27 2012

  • ASSURA DRC error file instance name & error location
    Hi , I have some problem with ASSURA DRC error file . The DRC run generates .err file which can be read by any standard text editor. The problem I am facing is from the text file, some instance names specially mosiacs are named in some strange manner . Also some of the locations of the the error is also...
    Posted to Custom IC SKILL (Forum) by Aritra on Tue, Oct 18 2011

  • How to perform Post-Layout simulations using UltraSim for Black-Box Cells?
    I hope you all are doing fine. I need some guidance regarding post-layout simulation of black-box digital cells from Artisan Standard Cell Library using Ultrasim. We have the verilog, lef and tlf files in the PDK along with CDB symbol database that we converted to OA database. We have imported verilog...
    Posted to Custom IC Design (Forum) by BraveHeart on Wed, Oct 12 2011

  • Any way to Abort Assura LVS run after input layers read ?
    We have a process with multiple variations that include slightly different input layers. To handle the variations within the same LVS file, we have switches. However, if a user is running process variation A and accidentally chooses the swtich to run variation B (having different input layers) , is there...
    Posted to Custom IC Design (Forum) by jm3395 on Wed, Mar 23 2011

  • Assura 4.1 Error Report and Probing
    Hi all, Up to now I have used Assura 3.0/3.1 for LVS and I was used to use the "Error Report" for probing problematic nets and devices. In fact this worked much better for me than the LVS Debug Enviroment. Now I have my first contact with Assura 4.1 and as it seems there is not probing capability...
    Posted to Custom IC Design (Forum) by baenisch on Mon, Nov 8 2010

  • Assura Directory Creation
    Hello, I'm new to Assura (in the past I used Hercules) and I have found the form quite annoying, so what I would like to is automatically load the Run Directory, while also create the Run Directory from cadence using the Library name and Cell Name. So what I was think is creating a bindKey that would...
    Posted to Custom IC SKILL (Forum) by Patrick1982 on Thu, Oct 28 2010
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