Home > Community > Tags > Assura/assura LVS
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Assura,assura LVS

  • LVS assura error "Unbound Pin"

    Hi, I'm currently completing my first layout, and getting errors on all my pins. When I run LVS I am getting an error on each saying "Unbound Pin". I have simply placed the pins that were automatically generated in layout XL (when I generated the layout from schematic) within the appropriate...
    Posted to Custom IC Design (Forum) by KipD on Tue, Feb 4 2014
  • How to perform Post-Layout simulations using UltraSim for Black-Box Cells?

    I hope you all are doing fine. I need some guidance regarding post-layout simulation of black-box digital cells from Artisan Standard Cell Library using Ultrasim. We have the verilog, lef and tlf files in the PDK along with CDB symbol database that we converted to OA database. We have imported verilog...
    Posted to Custom IC Design (Forum) by BraveHeart on Wed, Oct 12 2011
  • Any way to Abort Assura LVS run after input layers read ?

    We have a process with multiple variations that include slightly different input layers. To handle the variations within the same LVS file, we have switches. However, if a user is running process variation A and accidentally chooses the swtich to run variation B (having different input layers) , is there...
    Posted to Custom IC Design (Forum) by jm3395 on Wed, Mar 23 2011
  • Open Instance connections Assura LVS error

    Simple inverter as a Ring Oscillator Design is DRC clean but the Assura LVS brings up Nets Mismatch Tool...Open Instance Connections... I've tried severval ways to remove error but to no avail. Any insight will be appreciated. attach are the screen shot
    Posted to Custom IC Design (Forum) by jdgriggs on Mon, Oct 11 2010
Page 1 of 1 (4 items)