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Assura,Cadence

  • An urgent problem with the design rule check using Assura

    When I use Assura to do the design rule check after I have done layout using the C35B4 technology in Cadence, there is always a following probleme: [1] #INFO: C35B4/C35B3 ASSURA DRC DECK(REV9 DATE 26-Apr-2011) Last modified 15-Jun-2012. does anyone know why? Thank you advance for you response.
    Posted to Custom IC Design (Forum) by UUinfini on Fri, Jun 14 2013
  • Assura Directory Creation

    Hello, I'm new to Assura (in the past I used Hercules) and I have found the form quite annoying, so what I would like to is automatically load the Run Directory, while also create the Run Directory from cadence using the Library name and Cell Name. So what I was think is creating a bindKey that would...
    Posted to Custom IC SKILL (Forum) by Patrick1982 on Thu, Oct 28 2010
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