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Assura DRC rules

  • Assura: Include other files

    Hi everyone! Is it possible to split up an Assura rule file into several subfiles and include them into the main rule file which is loaded by the RSF-file? Calibre provides this feature and I really appreciate it for a clear structure. Thanks in advance! Regards!
    Posted to Custom IC Design (Forum) by PekkaH on Thu, Oct 4 2012
  • Re: Assura check the presence/absece of derived layer in if( )?

    Hi Quek, Thank you for your suggestion. Best regards, Mok
    Posted to Custom IC Design (Forum) by clmok on Sun, Apr 1 2012
  • Assura check the presence/absece of derived layer in if( )?

    Hi.. I am using Assura (4.1_USR2_HF10) for physical verification (with IC615). I wonder someone is using any work-around/alternative way to check the presence/absence of derived layer (dfII or gds) in if() function despite the tool contraint to check derived layer existing. For example. if( derived_layer...
    Posted to Custom IC Design (Forum) by clmok on Thu, Mar 29 2012
  • Assura selected rule checking

    Hi.. I am using Assura for physical verification (with IC61). It would be very helpful, I anybody can let me know, a way where I can check only few selected DRC rules instead of full DRC checking.. Thanks & Regards Vaibhav
    Posted to Custom IC Design (Forum) by VaibhavAR on Mon, Mar 26 2012
  • Re: Errors in ASSURA -- Cannot understand them

    Hi Queck, You are right. There are a lot of switches at the drc rule deck and I am trying to use them as to bypass the die-level verification. Thanks for all the help, Thodoros
    Posted to Custom IC Design (Forum) by Thodoros on Wed, Feb 1 2012
  • Errors in ASSURA -- Cannot understand them

    Hello, I tried to design several layouts in vortuoso with the umc 90nm technology and always after correcting a few others I end up with the same collection of errors. These are: 1. Rule No. 856 : Design_guideline2: NWEL overlap PFET diffusion edge is recommended to be not less than 0.5um However the...
    Posted to Custom IC Design (Forum) by Thodoros on Fri, Jan 27 2012
  • How to modify a automatically generated instance.

    Hi, After inductor cell generation (done with Passive Component Designer - PSD) I made DRC check, that found errors in the layout schematic. The problem is that some vias are placed too near to the edge of the polysilicon Patterned Ground Shield - PGD. I tried to remove the vias or correct the layout...
    Posted to RF Design (Forum) by pitter on Thu, Nov 5 2009
  • Re: saveDerived in Assura doesn't work

    Ingo, In Assura DRC saveDerived doesn't work. If you want to use saveDerived command then you should run from verify->DRC but here it will derive in that particular layout itself. Or if you want to use Assura to save in other layout you have to use RSF (RUN SPECIFIC FILE) where you can use "outfile"...
    Posted to Custom IC Design (Forum) by AmitBiswas on Sat, Jun 20 2009
  • saveDerived in Assura doesn't work

    Hi, I am trying to generate fill structures using Assura DRC and therefore want to output the derived layer to somewhere. I am trying to use the saveDerived rule to save it to the extracted view: saveDerived( m2fill ("m2fill" "drawing" ) ext_view ) But nothing happens. I tried copyGraphics...
    Posted to Custom IC Design (Forum) by janko on Fri, Jun 19 2009
  • Re: Assura DRC: How to Define derived layers

    Hi Stu, I don't work with Assura myself, but a few of my colleagues have stated that there does not appear to be any issue with the line of code as it is, but: 1) Ensure that the statement is in the Rules section, not in the layerDefs section 2) Ensure that the preceeding statement(s) do not have...
    Posted to Custom IC Design (Forum) by skillUser on Fri, Jan 30 2009
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