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Assertions,UVM

Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance

Do you want to enjoy the benefits of formal verification without having to become an expert? A newly archived Cadence webinar shows how you can do just that, using assertion-based verification IP (ABVIP) that supports both formal and dynamic verification of systems-on-chip using the ARM ACE protocol...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 19 2012
Panel: Mixed-Signal Designers Reveal “Gaps” and Solutions

Are we closing the gaps in mixed-signal design? That question was posed to five panelists, including three Cadence customer representatives, at the Mixed-Signal Technology Summit held at Cadence Sept. 20, 2012. While panelists noted progress in mixed-signal design tools and flows, they pointed to a number...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 1 2012
Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this...

Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Mon, Aug 27 2012
DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...

Posted to Industry Insights (Weblog) by rgoering on Tue, May 1 2012
CDNLive Silicon Valley 2012: Much More than Moore

Last week I had the pleasure of meeting dozens of customers at CDNLive! Silicon Valley, and learning from the keynotes, in-depth technical papers, and synchronistic conversations throughout the event. Below are some highlights and themes that emerged. Left to right: Keynote speakers Lip-Bu Tan (Cadence...

Posted to Functional Verification (Weblog) by jvh3 on Tue, Mar 20 2012
Event Report: Club Formal UK – Cache Coherency, UVM for ABV, and Brainstorming with R&D

Right before the December holidays it was my privilege to host the first "Club Formal" here in the U.K. My colleagues and I welcomed over 20 power users from 8 different companies, providing an exciting diversity of ideas and applications. We also took the opportunity to sneak preview some...

Posted to Functional Verification (Weblog) by TeamVerify on Tue, Jan 24 2012
Missing Real-World Assertions in Computer-Land

I was reviewing the page view statistics on the Cadence Functional verification blog and noticed that my previous three posts about missing real-world assertions are among the most read. So, in the spirit of milking the cash cow, I've collected a few more incidents that amused me with their utter...

Posted to Functional Verification (Weblog) by tomacadence on Mon, Sep 26 2011
Webinar Seeks to “End the Debate” – e or SystemVerilog?

Which language is best for functional IC verification - e or SystemVerilog? A newly archived Cadence webinar attempts to answer this question by analyzing the key capabilities in both languages, and presenting code comparisons that show how the same functionality would be expressed in either language...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 21 2011
Free Webinars Explore Advanced Functional Verification Techniques

UVM, assertion-based simulation, metric-driven verification, assertion synthesis, formal scoreboarding -- these are just a few of the advanced techniques that can improve your verification productivity. To help you learn about such techniques, Cadence is offering a series of nine free one-hour webinars...

Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 15 2011
Hot Topic: Should Separate Teams Handle Analog Verification?

Dedicated verification teams are well established in the digital world, but not in analog/mixed-signal design. Has the time come for separate analog verification teams? I've been following an ongoing debate on this topic in a couple of LinkedIn groups, a debate that followed my recent blog posting...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jul 21 2011

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Assertions,UVM

Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance

Panel: Mixed-Signal Designers Reveal “Gaps” and Solutions

Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

CDNLive Silicon Valley 2012: Much More than Moore

Event Report: Club Formal UK – Cache Coherency, UVM for ABV, and Brainstorming with R&D

Missing Real-World Assertions in Computer-Land

Webinar Seeks to “End the Debate” – e or SystemVerilog?

Free Webinars Explore Advanced Functional Verification Techniques

Hot Topic: Should Separate Teams Handle Analog Verification?