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Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!
TUTORIAL : Fast Track Your UVM Debug Productivity with Simulation and Acceleration Session: 5T on Thursday, Feb. 28 th from 8:30AM - 12:00PM For more details on the debug tutorial, click here This debug tutorial will highlight how customers can reduce their debug turnaround time by employing the most...
Posted to
Functional Verification
(Weblog)
by
Karnane
on Wed, Feb 20 2013
What Does it Take to Migrate from e to UVMe?
So you are developing your verification environment in e , and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Sep 5 2012
Analyzing Error Reports When Specman Crashes
One of the most frustrating events while running a tool would be to experience a tool crash. In Specman you would usually see something like: *** Error: OS signal 11 (segmentation violation) received See the stack trace in ./specman.err To debug: --------- o Rerun the same test with the same seed in...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Apr 17 2012
Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog
A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and Richard Goering from Cadence was posted on Cadence.com with the title: " Is e or SystemVerilog Best for Constrained-Random Verification? " This blog post has received much positive feedback from other Specman...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Jan 18 2011
My Reason For Choosing e – a Much More Advanced Verification Language. What’s Your Reason?
I'd like to share with you a story from many, many, many moons ago when I first evaluated e as a potential verification language solution for the company I was working for. At the time, our verification group was using the basic Verilog behavioural constructs for verification (memories to represent...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Jan 12 2011
2010 CDNLive Silicon Valley Photo Blog: Silicon Realization, ABV, OVM, MDV, Specman, Formal and More
If you are running short on time and can't view all the videos of the 2010 CDNLive Silicon Valley in San Jose, CA on October 26 posted here: www.cadence.com/cdnlive/na/2010/pages/default.aspx consider this photo blog as your very own "Cliff Notes" version. Click here to go to the gallery...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Tue, Nov 9 2010
Specman, e, and EDA360
The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward for Electronic Design" ; and for good reason - in 2010 the electronics world is finally starting to transform in ways that have been long anticipated by Specmaniacs and our "Trailblazer" program partners...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Jun 8 2010
When Less Is More, Part 3: Is e code really “infinitely” more compact than SystemVerilog?
Building on the packet generation example of part 1 , and the coverage examples of part 2 that compare the ratio of lines e code to lines of SystemVerilog for a given task, in this post I’m going to show you how to “divide by 0” and leverage e capabilities that simply don’t exist in SystemVerilog, technically...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Apr 21 2010
When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog?
In my last post I wrote some packet generation code to validate the claim that e code can be up to 3 times more compact vs. the equivalent functionality in SystemVerilog. The result was actually an e description that was more than 3x less than the SystemVerilog equivalent. In this post, let’s see...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Apr 6 2010
When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?
A famous expression in the software world is that “you can only expect 10 good lines of production code per day”. Web search for this phrase and you will see there is ongoing debate whether this figure is still only 10 lines, or it’s improved to 20, or 100, or more. One thing that’s...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Mar 30 2010
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