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Analysis

  • Calypto CEO Interview: Why System Realization Needs Sequential Analysis

    One important enabling technology of a transaction-level modeling (TLM) based design flow is an ability to verify the results of high-level synthesis. Calypto Design Systems , a member of the recently-formed Cadence System Realization Alliance , is playing an important role by closely integrating its...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 2 2010
  • HD2 and HD3 vs Frequency plot

    Hello, I am working in a line driver project. I have to plot 2nd and 3rd Harmonic Distortion vs frequency at the output node. Please guide me How to plot that Harmonic Distortion vs frequency curve
    Posted to Custom IC Design (Forum) by Verdhan on Wed, Jun 23 2010
  • Monte Carlo simulation puzzle

    Dear All, I know in Monte Carlo simulation, we can define the correlations between two devices. Now in the simulation, I have two instances of same module called "PGA", in the Monte Carlo simulation, I want to check the mismatch effect inside module "PGA", but I don't want to...
    Posted to Custom IC Design (Forum) by lunren on Sat, Mar 20 2010
  • Monte Carlo simulation correlations definition puzzle

    Dear All, I know in Monte Carlo simulation, we can define the correlations between two devices. Now in the simulation, I have two instances of same module called "PGA", in the Monte Carlo simulation, I want check the mismatch effect inside module "PGA", but I don't want any mismatch...
    Posted to Custom IC Design (Forum) by lunren on Thu, Mar 18 2010
  • How to identify version of simulator?

    Guys, In IC ver 610 , how to identify the version of simulator installed? and also list of simulators available? Please propose some easy way since I'm beginner in this software. Thank you very much. regards, M.Kumar
    Posted to Custom IC Design (Forum) by KumarMK on Wed, Feb 10 2010
  • Transient Noise Analysis | Noise File

    Hello, I am going to measure jitter of a VCO by means of Transient Noise Analysis. Simulation setup is not sophisticated, but I have some general questions though. I am using models of transistors that have been provided by PDK and they contain noise model too? In model setup dialog box (ADE) I can choose...
    Posted to Custom IC Design (Forum) by pitter on Wed, Nov 18 2009
  • North American SystemC User's Group Co-Located at DAC 2009

    We've been hearing about SystemC for a while. It's a great language! What's it great for? Well, you can find out from other users at the coming user group meeting co-located with DAC in San Francsico. This year promises to be full of excitement as the emergence of TLM 2, and many product...
    Posted to System Design and Verification (Weblog) by Steve Brown on Fri, Jul 17 2009
  • Input power of a subcircuit

    Hi, I'm simulating with an envlp + pss simulation a rectifier and I would like to estimate the power that goes in input to a subcircuit that implements it. The input voltage of the subcircuit is constant and the current is given by a constant plus an alternating contribution. I tried the following...
    Posted to Custom IC Design (Forum) by Ueue on Mon, Apr 6 2009
  • Error in Virtuoso..

    Hi all.. I got this error while designing, I have never encountered it before. Can anyone help me ? Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libinfineon_sh.so ... Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libnortel_sh.so ... Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libphilips_sh...
    Posted to Custom IC Design (Forum) by kgulur on Sat, Sep 27 2008
  • Change the threshold voltage ??

    Hi, I am a student working towards my Master's degree. I am currently doing a project where I have to design a low power circuit. The design consists of multi-Vt nmos and pmos. Can anybody help me out with this? How can I model a high Vt or low Vt transitor in Virtuoso. Although these cells are not...
    Posted to Custom IC Design (Forum) by kgulur on Fri, Sep 26 2008
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